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HTG-510: Altera Stratix V PCI Express Networking Card

The HTG-S510 series are powered by Altera Stratix V GXAx FPGA devices with different densities and resources in KF40-F1517 package. Designed  for high performance networking applications (i.e configurable/customizable 40Gbps NIC, 40Gbps network analyzer, etc.), these platforms provide access to two QSFP+ (40Gbps each) IEEE802.3ba compliant Ethernet ports, two SFP+ (10Gbps each) ports, 8-lane PCI Express Gen 3 (64Gbps), one high-speed mezzanine connector (FMC), two additional board-to-board connectors, two DDR3 SO-DIMMs (up to 8GB),  and three independent QDRII memory components (144Mb each).

Functionality of the HTG-S510 platforms are extended by one Vita57 compliant FMC (FPGA Mezzanine Connector) port providing access to  8 additional Serial Transceivers. HiTech Global offers wide range of FMC modules supporting these platforms for debugging, serial/parallel port expansion, etc. In addition, number of these platforms can be connected together in series through the FMC ports in either PCI Express or Stand-Alone mode.

Supported by 10G / 40G Ethernet, PCI Express Gen3, DDR3, and QDR-II reference designs along with PCI Express Linux/Windows drivers, the HTG-S510 minimizes engineering efforts for complex design integration and verification.

Supported Stratix V Devices:

Logic Elements (K) 425 622 840 1,052 462
Registers (K) 642 939 1,268 1,588 696
14.1-Gbps Transceivers 36 36 36 36 36
PCI Express Hard IP Blocks 1 or 4 1 or 4 1 or 4 1 or 4 1
Fractional PLLs 28 28 28 28 24
M20K memory blocks 2,304 2,560 1,600 2,016 1,950
Embedded Memory (MBits) 45 50 31 39 40
Variable Precision Multipliers (18×18) 512 512 1,000 1,500 2,966
Variable Precision Multipliers (27×27) 256 256 500 750 1,483
DDR3 SDRAM ×72 DIMM Interfaces 6 6 6 6 4
40G/100G PCS hard IP blocks Yes Yes No No No
User I/Os, Full-Duplex LVDS, 14.1-Gbps Transceivers
KF40-F1517 696, 174, 36 696, 174, 36 696, 174, 36 696, 174, 36 700, 175, 36

Hardware Key Features:

Altera Stratix V 5SGXA5, 5SGXA7, 5SGXA9, or 5SGXAB
x8 PCI Express Gen 3 edge connector (Root is also supported through HTG-FMC-PCIE module)
x2 QSFP+ IEEE802.3ba compliant Ethernet ports (40Gbps each)- or x8 SFP+ ports using the QSFP+ to SFP+ conversion cables
x2 SFP+ Ports (10Gbps each)
x2 DDR3 SODIMM sockets supporting up to 16GB of memory
x3 72Mb QDR-II SRAMs
x1 FMC Connector (8 serial transceivers)- HPC connector
x2 high-speed board to board connectors
PCI Express or Stand-Alone mode operation
9.5" x 4.25"

Ordering information
Part Numbers:
HTG-S5-PCIE-A5 - Price: [Contact us]
HTG-S5-PCIE-A7 - Price: [Contact us]
HTG-S5-PCIE-A9 - Price: [Contact us]
-HTG-S5-PCIE-AB - Price: [Contact us]

Kit Content:
- HTG-S510 Board
- Hardware Setup Guide
-  User Manual, Schematics (in searchable pdf format) , frame work demo files, PCI Express Gen 3 design , DDR3 and QDR II memory controllers

The Extensible Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface components, device drivers and APIs for the HTG-S510 platform. The EFW eliminates the tedious and time consuming phase of module bring-up by providing module targeted and hardware verified physical interfaces for the HTG-S510. Additionally, the framework allows the user to simulate, integrate and test Ethernet and DMA cores (licensed separately) with the cost-free time limited synthesizable binaries and simulation libraries. 

Following figure shows the elements and interfaces of the S5-PCIe framework.

The base framework provides all the design files, device drivers and API to access the memory mapped registers inside the FPGA. It enables an end user to instantiate and control custom logic blocks through the GUI application.

EFW implements the capability to program and erase the P30 parallel flash memory on the HTG-S510 through the PCIe interface at very high speeds. Integrating the remote upgrade unit allows any user design to be field upgradeable through PCIe. It can also eliminate the need for the USB platform cable during the design and development phase.  

The base framework also provides the targeted (Quartus generated) wrapper for the 1333Mbps (667MHz) DDR3 and 350MHz QDRII+ controllers. Memory mapped I2C controllers are also integrated in the EFW to control and configure the PHYs and clock elements on HTG-S5-PCIE module. 

EFW also serves as the evaluation platform for the 10G low-latency and 40G Ethernet IP solutions. It allows the user to test the 10G and 40G Ethernet interface capabilities of the HTG-S510 without any code development.    User can then extend the Ethernet interfaces to user specific designs through the Altera’s Avalon-ST streaming interface. Full simulation libraries included in the EFW enables the user to simulate and test the Ethernet interfaces before licensing the solutions.

EFW’s integrated (time limited) 4-channel 128-bit data path (@ 250MHz) block DMA controller along with the PCIe device drivers allows the user to implement and verify high speed data and packet applications on the HTG-S5-PCIE module. 

Key Features

·   Framework includes module targeted  and hardware verified RTL blocks for:

o  x8 Gen2 PCIe hard IP block with PCIe application interface and arbiter

o  Avalon-MM master/arbiter for distributed control and configuration of various EFW blocks

o  Two 667MHz/1333Mbps DDR3 controllers

o  Three 350 MHz QDRII+ controllers  

o  Remote flash upgrade unit with standard host interface for in-system field upgrade of the FPGA image through the PCIe interface 

o  I2C controllers

o  Reconfiguration block for run-time control and configuration of the serial transceivers

·   Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Ethernet solutions up to 40Gbps:

o  40Gbps Ethernet using the direct QSFP+ interface

o  10Gbps Low Latency Ethernet using the SFP+ interface

·   Time limited (30min) synthesizable binaries and full simulation libraries for  hardware verified 128-bit data path Multi-channel (4) scatter-gather block DMA controller

·   All modules with Altera’s Avalon-ST streaming interface for data path and Avalon-MM interface for control, configuration and memory interface

·   Top level RTL interface wrapper for custom user design block for easy implementation of user logic

·   Linux device drivers and API for PCIe interface

·   A single unified GUI for entire FEW with scripting support
Accessories (FMC Modules)

Dual14-bit ADC (3 GSPS)/ Dual 16-bit DAC (12.6 GSPS) FMC Module 
More info..

Quad 16-bit DAC
FMC Module
More info.

Quad 16-bit ADC
FMC  Module
More info..

x4 SFP+

FMC Module

More Info..

x10 SFP+ 

FMC Module

More info..

x8 SMA / x33 LVDS

FMC Module

More Info.

x6 QSFP28 / QSFP+ FMC+ Module
More info..

2-port QSFP28/
QSFP+ 56G) FMC Module
More Info..

 FMC+ Module
More info..

x2 SFP/x1 QSFP+
 FMC Module

 More info..

x2 QSFP+ 
FMC Module
More Info..

x2 SFP+ /10G PHY
FMC Module
More info..

42-channel RS485/RS422
FMC Module
More Info..

x8 PCIE RC  
 FMC Module
More info..

U.2 (SFF-8639)/Display Port/ SATA/ Ethernet / USB FMC Module
More info..

x4 RJ45   (SGMII)
FMC Module
More Info..

2x300G (or 6x100G) LEAP FMC Module
More info..  

2GB or 4GB Hybrid
 Memory Cube (HMC)
FMC Module More info...

x4 SATA/ x4 SFP+  (double-size)
FMC Module
More Info..

x8 SMA (double-size)
 FMC Module
More Info..

24-port  Mini SMP/GPPO/ 34-pair LVDS
FMC Module
More info..

Gearbox QSFP28
FMC Module
 More info..

Carrier board to daughter card and carrier board
to carrier board
FMC cable
More Info..

x4 SMA
FMC Module
More Info..

x2 CXP  (12x12G+)
FMC Module
More info...