Virtex 4 LX60 based ARM926 Evaluation Board

V4IP-500 : Xilinx Virtex 4 LX60 & ARM926/1136 Verification IP Platform

The Xilinx^® Virtex 4 Verification IP Platform (V4IP-500) provides an AMBA ^TM Multi-layer AHB environment which enables system-on-chip (SoC) developers to prototype complete systems, prove custom IP, and develop and test device drivers for custom IP Cores . The Virtex 4 LX60 device is connected to ARM926EJ- S or ARM1136JF- S Core Tile and may be stacked to provide additional capacity. High performance and high pin-count interconnect allows large design prototyping.

The Xilinx Virtex 4 Verification IP Platform can be used for HW/SW Co-design and verification IP Cores such as MPEG4, H.264, Audio Code 97, CMOS Image Sensor, Color TFT LCD, USB 2.0 , and more.

ARM926EJ-S, ARM 1136 Core Tiles

The Core Tile for ARM926EJ-S / ARM1136JF-S contains an ARM926EJ-S/ARM1136JF-S processor inside a test chip. The processor’s configuration signals and a multiplexed AHB bus are connected to the board’s headers, so that systems based on this core can be easily prototyped. These boards can be stacked together to implement complex custom systems. The CPU core frequency can be adjusted up to 200MHz, but the maximum frequency depends upon the test-chip fitted. Core Tiles can not be used stand-alone.

ARM926EJ-S / ARM1136JF-S processor test chip
AMBA AHB Bus HDR X/HDR Y/HDR Z
High density stacking connectors
JTAG connection for processor run control and debug
Mictor connectors for Trace equipment
ARM926EJ-S/ARM1136JF-S

Xilinx FPGA
ISE Design Tool

Xilinx PlanAhed

Item	Specifications
SoC Processor	ARM Core Tile Interface connector
SoC Processor	Options (should be purchased from ARM) - Core Tile for ARM926EJ-S (Versatile/CT926EJ-S) - Core Tile for ARM1136JF-S (Versatile/CT1136JF-S)
FPGA	One Xilinx Virtex 4 LX60 FF1148 - 5Million Gates (V4IP-1000 is available with two LX60 FPGAs)
AMBA Bus	AHB 133 MHz
High Speed Memory	- PC100/PC133 64MB/128MB SDRAM - 32/64 MB FlashROM - 2 MB Asynchronous SRAM
Communication	2-ch UART
	USB 1.1 Host/Client and the USB 2.0 PHY for multimedia and tools connection
	One 10/100 Ethernet
Video	3.5" TFT-LCD supporting 16-bit Color
	640x480 CMOS Image Camera Module interface
	CAM-Link (Camera Link) - Ver. 1.1 Specification - LVDS Channel Link
Audio Codec	AC97 Audio Codec
I/O	User Push Bottom Switch * 8
I/O	Reset Signal
AHB Mictor Connectors	7 Mictor Connectors
External I/O slot	1 Expansion Slot from FPGA LX60 200pins ( Connector )
SD/MMC	SD/MMC socket only
CF Card Configuration	Xilinx SystemACE
Debugging and Configuration	20-pin MultiICE port for ARM Core Tile
Download Port	JTAG port for FPGA
Download Port	Xilinx Platform Flash (XCF32P*2)
Accessories	JTAG Cable
	Two 9-pin female-to-female null modem cables
	Power Cable 220V or 110V
	Aluminum Case
	User Manual
Power Supply	Micro-ATX PC Power Supply 220V/110V AC

Optional Modules:

Item	Specifications	Comments
SoC Processor	ARM RealView○R ARM926EJ Core Tile™	Contact us
SoC Processor	ARM1136EJ Core Tile™	Contact us
AD/DA Option Module	4CH ADC(125MSPS) / 4CH DAC(165MSPS)	Contact us
Video	640x480 CMOS Image Camera Module	Contact us

Testing and TLM IP Cores

The following IP Cores can be used for testing and TLM (Transaction Level Modeling). The V4IP Board does not directly support these IP cores and a wrapper logic should be added by the designers.

No	IP Name	Lang.	Description
R-1	ahb2ahb_reg_sync	VHDL	AHB2AHB Registered Output Bridge
R-2	ahb2ahb_sync	VHDL	AHB2AHB Pass through Type Bridge
R-3	ahb2apb_p6	VHDL	AHB2APB 6-Slave Bridge
R-4	ahb2apb_p8	VHDL	AHB2APB 8-Slave Bridge
R-5	ahb2tri	VHDL	Tri-state AHB Bus Bridge
R-6	ahb_bus_matrix_m1s8	VHDL	AHB Bus Matrix (1 Master, 8 slave)
R-7	ahb_bus_matrix_m2s3p	VHDL	AHB Bus Matrix (2 Master, 3 slave, priority)
R-8	ahb_bus_matrix_m2s4r	VHDL	AHB Bus Matrix (2 Master, 4 slave, round robine)
R-9	ahb_bus_matrix_m3s2p	VHDL	AHB Bus Matrix (3 Master, 2 slave, priority)
R-10	ahb_bus_matrix_m3s2r	VHDL	AHB Bus Matrix (3 Master, 2 slave, round robine)
R-11	ahb_bus_matrix_m3s2rp	VHDL	AHB Bus Matrix (3 Master, 2 slave, priority+rr)
R-12	ahb_bus_matrix_m3s4rp	VHDL	AHB Bus Matrix (3 Master, 4 slave, priority+rr)
R-13	ahb_bus_matrix_m3s5rp	VHDL	AHB Bus Matrix (3 Master, 5 slave, priority+rr)
R-14	ahb_bus_matrix_m4s2r	VHDL	AHB Bus Matrix (4 Master, 2 slave round robine)
R-15	ahb_bus_matrix_m4s3rp	VHDL	AHB Bus Matrix (4 Master, 3 slave, priority+rr)
R-16	ahb_bus_matrix_m4s4r	VHDL	AHB Bus Matrix (4 Master, 4 slave round robine)
R-17	ahb_bus_matrix_m4s4rp	VHDL	AHB Bus Matrix (4 Master, 4 slave, priority+rr)
R-18	ahb_bus_matrix_m4s5r	VHDL	AHB Bus Matrix (4 Master, 5 slave round robine)
R-19	ahb_bus_matrix_m4s6r	VHDL	AHB Bus Matrix (4 Master, 6 slave round robine)
R-20	ahb_bus_matrix_m4s8r	VHDL	AHB Bus Matrix (4 Master, 8 slave round robine)
R-21	ahb_bus_matrix_m5s5rp	VHDL	AHB Bus Matrix (5 Master, 5 slave, priority+rr)
R-22	ahb_bus_matrix_m5s6rp	VHDL	AHB Bus Matrix (5 Master, 6 slave, priority+rr)
R-23	ahb_bus_matrix_m6s5rp	VHDL	AHB Bus Matrix (6 Master, 5 slave, priority+rr)
R-24	ahberr_monitor	VHDL	AHB Error Transaction Monitor
R-25	ahbswitch2r	VHDL	AHB Switch, 1 Source, 2 Destination
R-26	ahbswitch2p	VHDL	AHB Switch, 1 Source, 2 Destination (Preemptive)
R-27	ahbswitch3p	VHDL	AHB Switch, 1 Source, 3 Destination (Preemptive)
R-28	ahb_dummy_master	VHDL	AHB Dummy Master
R-29	ahb_dummy_slave	VHDL	AHB Dummy Slave
R-30	apb_dummy_slave	VHDL	APB Dummy Slave
R-31	arm7s_cache	VHDL	ARM7TDMI Cache
R-32	async_sram_ctrl_ahb	VHDL	Asynchronous SRAM Controller (AHB Data, AHB Ctrl)
R-33	async_sram_ctrl_apb	VHDL	Asynchronous SRAM Controller (AHB Data, APB Ctrl)
R-34	counter	VHDL	Counter (APB I/F)
R-35	ebi32	VHDL	External Bus Interface (AHB Data, AHB Ctrl)
R-36	i2c	VHDL	I2C Interface (APB I/F)
R-37	integrator_mux	VHDL	ARM Integrator Control/Data Multiplexer
R-38	intr_ctrl	VHDL	Interrupt Controller (APB I/F)
R-39	ahbcfgmem	MT1/FLI	Simulation Purpose Configurable Memory (AHB I/F)
R-40	ahbmem	MT1/FLI	Simulation Purpose Memory (AHB I/F)
R-41	apbmem	MT1/FLI	Simulation Purpose Memory (APB I/F)
R-42	cfgmem	MT1/FLI	Simulation Purpose Memory (SRAM I/F)
R-43	dpssram	VHDL	Dual Port Synchronous SRAM (Simulation Model)
R-44	pzbtssram	VHDL	Pipelined ZBT SSRAM (Simulation Model)
R-45	sram	VHDL	SRAM (Simulation Model)
R-46	sram16	VHDL	SRAM, 16 bit Data (Simulation Model)
R-47	ssram	VHDL	SSRAM, bidirectional data I/O (Simulation Model)
R-48	ssram_u	VHDL	SSRAM, unidirectional data I/O (Simulation Model)
R-49	zbtssram	VHDL	ZBT SSRAM (Simulation Model)
R-50	dual_onchip_ssram_ctrl_vdp	VHDL	SSRAM Controller, Virtual dual port with two SPSSRAM
R-51	onchip_ssram_ctrl_vdp	VHDL	SSRAM controller, Virtual dual port with one SPSSRAM
R-52	onchip_ssram_ctrl	VHDL	On-Chip SSRAM Controller (AHB I/F)
R-53	resetgen	VHDL	Peripheral Reset Generator (AHB I/F)
R-54	signal_tracer	VHDL	On-Chip Signal Tracer
R-55	smdma	VHDL	Single Master DMA Controller (AHB I/F)
R-56	tftlcdctrl	VHDL	TFT-LCD Contreoller (AHB I/F)
R-57	timer	VHDL	3-Channel Timer (APB I/F)
R-58	Uart	VHDL	UART (APB I/F)
R-59	virtual_panel	MT1/FLI	Virtual TFT-LCD Panel model
R-60	virtual_rs232	MT1/FLI	Virtual UART Terminal Emulator
R-61	sdram_ctrl	VHDL	SDRAM Controller (AHB I/F)
R-62	ddr_sdram_ctrl	VHDL	DDR SDRAM Controller (AHB I/F)
R-63	ac97_apb	VHDL	AC97 Interface (APB I/F)
R-64	ps2_apb	VHDL	PS/2 Interface (APB I/F)
R-65	i2s_apb	VHDL	I2S Interface (APB I/F)

Ordering Information:

- Part Number: V4IP-500
- Price: $6,900 (USD)

How To Buy

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San Jose, CA 95124 USA
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