ASIC Prototyping with multi Virtex-5 LX330 FPGAs

The HTG-RPS-7000 is a high-speed, well-designed prototyping platform for all ASIC/SOC prototyping and hardware/software co-verification. This platform provide generous FPGA gates, IOs, memory, and main stream peripherals. The HTG-RPS-7000 platform is carefully designed for maximum performance and the best signal integrity in all layers. All signals to connectors and between FPGAs are length matched, thus minimizing skew and allowing very high speed signaling.

The HTG-RPS-7000 offers maximum flexibility so the board can be reused in several projects or configurations by simply replacing optional boards containing I/O and custom subsystems. Several option daughter boards are available to provide additional application-specific resources like processors, memory devices, PCI express interfaces etc.

Different ARM Coretile modules can be used on the HTG-RPS-7000 platform

► 4 on-board (soldered) Xilinx Virtex-5 XC5VLX330FF1760-1 FPGAs

- 8 million ASIC gates

► Inter-FPGA Connection

      - FPGA-A ↔ FPGA-C : 293 pin
      - FPGA-A ↔ FPGA-B : 295pin
      - FPGA-B ↔ FPGA-D : 293 pin

- FPGA-C ↔ FPGA-D : 25 pin

► Total 2,942 IOs

- FPGA-A : DMC(140), SMC(130), CTI1(166), CTI2(165)

- FPGA-B : CON2(140), CON4(130), CTI1(166), CTI2(165)

- FPGA-C : CON1(150), CON2(150), CON3(150), CON4(150), CON5(150),

CON6(120)

- FPGA-C : CON1(150), CON2(150), CON3(150), CON4(150), CON5(120),

CON6(150)

► VCCs can be set individually

- VCC_TILE VCC_DMC, VCC_FB_CON2,

- VCC_FC_CON (1,2,3,4,5), VCC_FD_CON (1,2,3,4,6)

- VCC_SMC, VCC_FB_CON4, VCC_FC_CON5, VCC_FD_CON6 : 3.3V fixed

- Each region can individually be adjusted to: 3.3, 2.5, or 1.8 V or sourced
externally for other voltages

► User IO Connectors:
- 4 user I/O connectors : FPGA -A & FPGA-B
- 6 user I/O connectors : FPGA -C & FPGA-D

► Well-designed supply to provide power for:

- 4 FPGAs (Maximum Speed LVDS)

- Each Device module (Memory, Peripherals)

► I/O voltage of memory connector on FPGA-A can be set individually for connection of various dynamic memory devices including LPDDR

► To offer maximum speed, each on-board FPGA has individual clock source which its path delay can be configurable with ISP Clock 5620A.

► ARM CT/LT (for Core) Board Interface

► 4 Global Clock from ISPCLK5620

- Clock skew control possible

► One external clock source (SMA Connectors)

► FPGA/ASIC Prototyping

► Support ARM926EJ-S, ARM1176 etc

► Support AMBA 2.0 AHB and 3.0 AXI

► Power Distribution Logic, Clock Distribution Logic

► Signal group(FPGA2FPGA) connection, Connector connection

Skew matching (within 500ps) and Impedance Matching

► FPGA Configuration

- On-Board SystemACE Configuration

- JTAG

► ATX POWER supply

► On-board temperature and voltage watchdog

► Temperature controlled fan drivers (Chip)