Xilinx Virtex™ -6 HXT 8-lane PCI Express /4-port SFP+ Optical Network Card



Powered by Xilinx Virtex-6 HX565Tor HX380T FPGA (with 40 GTX (6.6Gbps) & 24 GTH (11.13Gbps) serial transceivers), this optical network card provides access to eight lanes of PCI Express Gen 2 , four SFP+ connectors (40 Gbps), MoSys Bandwidth Engine® IC (576Mb Multibank 1T-SRAM with Serial 10G Interface and onboard ALU), up to 16 GB of DDR3 SO-DIMM, QDR II, ten 11.18 Gbps  and ten 6.6Gbps serial ports. The on-board FPGA Mezzanine Connectors (FMC) along with off-the-shelf FMC modules, expend the functionality of the board for variety of different applications.

Two SFP+ ports are powered by an external PHY chip (with Electrical Dispersion Compensation) supporting short range, medium range, and long range optical interfaces. Two additional SFP+ ports are connected directly to the GTH transceivers of the on-board FPGA.



Xilinx Virtex-6 HX380T or HX565T FPGA
x8 PCI Express Gen2 Edge Connector
x2 SFP+ ports with Electrical Dispersion Compensation (EDC) & CDR support through external PHY chips (ideal for Long Range applications)
x2 SFP+ ports with direct interfaces to the on-board  FPGA's GTH (10G) serial transceivers (ideal for Short Range applications)
MoSys Bandwidth Engine® IC (576Mb Multibank 1T-SRAM with Serial 10G Interface and onboard ALU)
x2 DDR-3 SO-DIMM (up to 16GB)
x2 QDR-II Components (each 4Mx18)
x2 FPGA Mezzanine Connectors (FMC)
  - FMC #1: 9 LVDS I/Os and 10 GTH (11.18 Gbps) Serial Transceivers
  - FMC # 2: 34 LVDS I/Os and 10 GTX (6.6 Gbps) Serial Transceivers
  Configuration through JTAG or CPLD
  ATX and DC power supplies for PCI Express and Stand Alone operations
  LEDs & Pushbuttons
Size: 9.5" x 4.0"


PCI Express Driver Source Code (C) - Windows XP or Linux     

- PCI Express Back End (High Performance DMA Engine) 

Kit Content:

- Hardware Setup Guide
- CD ROM with User Manual, Schematics (in searchable pdf format) , Software Drivers (eval.), PCI Express Gen 2 CoreGen PIO design , ChipScope PRO IBERT reference/test designs, Xilinx MIG based DDR3 and QDRII memory controllers

Ordering information

Part Numbers:

HTG-V6HXT-X8PCIE-380-2 (populated with XC6VHX380T-2FFG1923 FPGA)
HTG-V6HXT-X8PCIE-380-3 (populated with XC6VHX380T-3FFG1923 FPGA)
HTG-V6HXT-X8PCIE-565 (populated with XC6VHX565T-2FFG1923 FPGA)

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Reference Designs:

Extensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface components, device drivers and APIs for the HTG-V6HXT-X16PCIE platform. The EFW enables end user to skip the tedious and time consuming phase of the platform's bring-up by providing targeted and hardware verified physical interfaces.

Additionally, the framework allows users to simulate, integrate and test Ethernet and DMA cores (licensed separately) in their designs with time limited synthesizable binaries and simulation libraries. 

Following figure shows the elements and interfaces of the framework.

The base framework provides all the design files, device drivers and API to access the memory mapped registers inside the FPGA. It enables an end user to instantiate and control custom logic blocks through the GUI application.

Another key feature of the base EFW is the capability to program and erase the G18 BPI memory on the HTG-V6H-x8PCIE through the PCIe interface at very high speeds. Integrating the Field Upgradable  controller allows any user design to be field upgradeable through PCIe. It can also eliminate the need for the USB platform cable during the design and development phase.  

The base framework also provides the targeted (MIG generated) wrapper for the 1066Mbps (533MHz) DDR3 and 350MHz QDRII+ controllers. Memory mapped MDIO and I2C controllers are also integrated in the EFW to control and configure the PHYs and clock elements on HTG-V6H-x8PCIE module. 

EFW also serves as the evaluation platform for the 10G low latency and dual-mode 10G/1G Ethernet IP solutions. It allows the user to test the 1G and 10G Ethernet interface capabilities of the HTG-V6H-x8PCIE without any code development. User can then extend the Ethernet interfaces to user specific designs through the industry standard AXI4-Streaming interface. Full simulation libraries included in the EFW enables the user to simulate and test the Ethernet interfaces before licensing the solutions.

EFW’s integrated (time limited) 4-channel 128-bit data path (@ 250MHz) block DMA controller along with the PCIe device drivers allows the user to implement and verify high speed data and packet applications on the HTG-V6H-x8PCIE module. 

Key Features

·   Framework includes module targeted  and hardware verified RTL blocks for:

o  x8 PCIe Gen2 hard IP block with PCIe application interface and arbiter

o  AXI4-Lite master/arbiter for distributed control and configuration of various EFW blocks

o  Two 1066Mbps/533MHz DDR3 controllers

o  Two 350 MHz QDRII+ controllers

o  Field upgradeable flash (FUp) controller for in-system field upgrade of the FPGA image through PCIe interface 

o  MDIO and I2C controllers

o  DRP controller for run-time control and configuration of the GTH Transcievers

·   Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Ethernet solutions up to 10Gbps:

o  10Gbps Low Latency Ethernet using the SFP+ interface on the module

o  Dual Mode 10G/1G Ethernet using the SFP+ interface on the module

·   Time limited (30min) synthesizable binaries and full simulation libraries for  hardware verified Multi-channel (4) 128-bit data path scatter-gather block DMA controller

·   All modules with industry standard AXI-4 streaming interface for data path and AXI-4 Lite interface for control, configuration and memory interface

·   Top level RTL interface wrapper for custom user design block for easy implementation of user logic

·   Linux device drivers and API for PCIe interface

·   A single unified GUI for entire EFW with scripting support

Accessories & Tools

FMC daughter card with  one QSFP+ and two SFP+ connectors with default clocks for CPRI/OBSAI (other clocks can also be supported)
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FMC daughter card with two SFP+ connectors, two 10Gbps physical layer transceivers which provide full PCS, PMA, and XGXS sub-layer functionality

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FMC daughter card with two CX4/Infiniband connectors providing access to two 10Gig ports

Part Number:
Price: $595


FMC daughter card with one CX4, two SATA, and two SMA ports

Part Number:
Price: $545

FMC daughter card with x8 PCI Express Root interface

Part Number:
Price: $695

FMC daughter card with 8 SMA ports and pin headers providing access to 33 LVDS/66 Single-ended IOs
Part Number:
Price: $595

FMC daughter card with four SFP/SFP+ and four SATAI/II/III connectors.

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FMC daughter card with 32 SMA connectors for 8 serial transceiver ports, two SMA connectors for external clock, and on-board super clocks

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FMC to FMC Cable

Part #: FMC-TO-FMC-9 (9" length)
(5" length)

FPGA Programming Cable (USB)
Part #: HW-USB

PCI Express Test Module & Serial IO Expander
Part Number: HTG-PCIE-TEST
Price: $695

HiTech Global, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124   USA

Tel : + 1 408 781-7778 
Fax: + 1 408 268-4173