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Main Specification:
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F-Sight PowerPC |
F-sight MicroBlaze |
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Devices supported |
Xilinx Virtex-II Pro, Virtex-4
FX, and Virtex-5 FXT with hard-coded PowerPC 405 or PowerPC 440 Processors |
Virtex-II / Virtex-II Pro / Virtex-4 / Virtex-5
Spartan-3 / Spartan-3L / Spartan-3E / Spartan-3A |
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Target interface
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Pins used |
FPGA dedicated JTAG interface |
JTAG I/F specifically for FPGA (Essential), Analyzer measuring
pin (Optional) |
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FPGA |
Voltage |
Auto trace (2.0V and 3.6V) |
Auto trace (1.2V and 3.6V) |
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JTAG clock
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150KHz, 1MHz, 5MHz, 10MHz, 20MHz or 30MHz
|
150KHz, 1MHz, 5MHz, 10MHz, 20MHz or 30MHz
|
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Chain devices |
Up to 8 (The sum of the JTAG instruction lengths
must be no more than 128 bits.) |
Up to 8 (Including CPU) |
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Pins used |
I/O pins are assigned with JTAG I/F and CPU tracing signals |
- |
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CPU |
Voltage |
Auto trace (1.2V and 3.6V) |
- |
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JTAG clock
|
1MHz to 40MHz |
- |
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Current Consumption |
50uA or less |
|
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Voltage Measurement |
Measurement display based on
sampling with 50 mV precision. Values displayed to two decimal
points. |
Measures by sampling and shows the results with accuracy of 50mV
and precision showing 2 decimal places |
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Connector |
38-pin Mictor connector |
38-pin Mictor connector |
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FPGA
|
Tools supported |
ISE 8.1i/EDK 8.1i, ISE 8.2i/EDK 8.2i, ISE 9.1i/EDK
9.1i, ISE 10.1i/EDK
10.1i |
ISE 8.1i/EDK 8.1i ISE 8.2i/EDK 8.2i ISE 9.1i/EDK
9.1i
ISE 10.1i/EDK 10.1i |
|
Language supported |
VHD and Verilog |
VHD and Verilog |
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Probing function |
Automatically routes FPGA internal nodes to FPGA
pins. |
Automatically routes FPGA internal nodes to FPGA
pins. |
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Readback function
|
Sampling display for internal nodes and block RAM
contents |
Sampling display for internal nodes and block RAM
contents |
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Linkage function |
Loads ISE in the background and automatically
executes from synthesis through configuration |
Loads ISE in the background and automatically executes from
synthesis through configuration |
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CPU
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Execution control
|
Program execution, Stop, Step execution, Trace
execution, Come execution |
Program execution, Stop, Step execution, Trace
execution, Come execution - Debugging Mode: OPB_MDM |
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Register, Memory
|
Reference to/change to register and memory,
download to memory during a break |
Supports referencing/editing of register and memory and
downloading to memory during break. |
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Software break |
256 points |
56 points |
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CPU break |
Program : 4 points - Data : 2 points |
By setting hardware debug logic when building MicroBlaze with
EDK. |
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Flash memory |
Various debug functions such
as download to flash memory, software break specification and
memory rewrite function are supported. A new device can be added
easily by using the definition file. |
Various debug functions such
as download to flash memory, software break specification and
memory rewrite function are supported. A new device can be added
easily by using the definition file. |
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Execution Time Measurement |
Measures execution time of the user program (64-bit counter,
measurement unit=1uS) |
|
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Trace function
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Capacity |
512K cycles |
512K cycles |
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Sampling clock |
Max 200MHz |
Max 200MHz |
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Threshold settings |
Can be specified between 0.3 V and 2.2 V in 0.1 V increment. |
Can be specified between 0.3 V and 2.2 V in 0.1 V increment. |
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Trigger settings |
CPU event, Analyzer pattern condition, Edge
specification |
Analyzer pattern condition, Edge option |
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Trigger position |
5 positions between START and END |
Any of 5 positions between START and END can be specified. |
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Trigger mode |
Trigger stop, Trigger break |
Trigger stop, Trigger break |
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Channels |
16 channels (8 channels of which are for CPU
tracing) as standard plus 32 channels for optional expansion |
32 channels for optional expansion |
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Time stamp function |
10nS or 1μS |
10nS or 1μS |
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Standard debugger
|
CSIDE for F-Sight 2VP-PPCE-E |
CSIDE for F-Sight MicroBlaze-E |