Xilinx PlanAhead Design Tool

                                                                                                                                                           

PlanAhead streamlines the step between synthesis and place-and-route to give designers more control and insight into how designs are implemented to achieve their target Fmax with fewer design iterations. The tool allows designers to utilize a hierarchical design methodology to minimize routing congestion, simplify clocking and interconnect complexity, and explore implementation options. Recent customer benchmarks yielded average Fmax performance improvements of 30 percent relative to competing FPGAs, which translates to an average of two speed-grade performance and cost advantage for customers. Complex, multi-clock, high-utilization designs yielded improvements of 56 percent on average over competing solutions.

PlanAhead 8.1 delivers improved quality of results by providing a unique solution to the problems of:

  • Routing congestion and/or unpredictable routing results
  • Tightly packed designs with heavily constrained interconnect
  • Clock complexity
  • Paths-spanning hierarchy
  • Inconsistent performance level

With PlanAhead 8.1, Xilinx provides the industries first front-to-back solution for designers looking to simplify the complexities of Partial Reconfiguration. Partial Reconfiguration is a process of device configuration that allows a limited, predefined portion of an FPGA to be reconfigured while the remainder of the device continues to operate.
 

Key Features:
  • Hierarchical, block-based, incremental design methodology
  • New ExploreAhead allows designers to manage multiple implementation strategies for optimal results
  • Metric Maps allow visual exploration and rapid identification of problem areas within the design
  • TimeAhead, an internal static timing engine, allowing examination of a design’s feasibility relative to timing
  • Automatic and physical block sizing and placement
  • IP Re-Use and Teamwork Design
  • Connectivity, timing, and utilization analysis
  • Clock I/O and clock region planning
  • Gate-level floorplanning allowing fine tuning of placement
  • Graphical display of important design metrics

Part Number: DO-PLNHD
Price: $4,995

 

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