Semulator : Simulator Controlled Emulation

Today's FPGA development includes Simulation of the HDL- Functional blocks, FPGA synthesize, and test in a rapid prototyping system. SEmulation combines the two steps and allows the step-by-step transfer of the functional blocks from the simulator (software) into the FPGA (hardware), so without leaving the development environment the simulations and thus the development time will be shortened.

Currently the Simulation and Emulation environments are separate and not always compatible. This results in engineering time being wasted getting simulated code to run in the emulator environment. Using the SEmulator, mistakes and insecurities are excluded as we simulate on the target hardware. The SEmulator also allows designer to introduce into the simulation any external component, (this is “hardware in the loop”). For the developer this means functional “First Silicon” and therefore a reduction of development costs, as well as an increased reactivity on market requirements

Bridging the gap between Simulation and Emulation

SEmulator is a made-up word that combines the words Simulator and Emulator. It describes the basic functionality of the SEmulator very well. The SEmulator provides bridging functionality between the domain of digital hardware simulation and the world of FPGA prototyping. Design blocks can easily be moved between this two domains.

The real aim for the hardware designer is not the simulation. It’s running the design on real hardware. The step from simulation to the real hardware prototype is a huge one and should not be underestimated. When the simulation results are satisfactory, the designer takes the whole design and downloads the synthesized Netlist into an FPGA prototyping board. Then a logic analyzer in needed to locate and fix any bugs in the design. The SEmulator approach enables the designer to use the prototyping FPGA board at an early state of the design flow. The SEmulator allows design blocks to be moved into the FPGA and to co-simulate them with the actual developed design blocks in the HDL simulator.

Advantage of Semulation:

• Early and continued testing of final hardware- Higher design security
• Dramatically decrease RTL simulation time - Decrease development time
• Standard FPGA board for development, different boards available -  No additional hardware cost
• Hardware in the Loop (Co-simulation) - Every external hardware can be implemented easily in the SEmulator
• No limitation on pin and gate count - Broad family concept – Many extension boards

Requirements:

• A standard FPGA development system e.g. Hpe_midi
• A PCI Express communication card e.g. Hpe_com1
• Software package Hpe_desk - includes SEmulator, Clock Factory Programmer, JTAG Scanner, ALTERA Quartus
• A  PC and MENTOR Modelsim

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