Vita 57 provides a mechanical
standard for I/O mezzanine modules. This standard introduces a
methodology that shall allow the front panel IO of IEEE 1101 form factor
cards to be configured via mezzanine boards. Vita 57 modules have fixed
locations for serial/parallel IOs, clocks, Jtag signals, VCC, and GND.
HiTech Global's Vita 57 modules can be plugged into any Vita 57
compliant carrier boards.
This FMC module is
supported by two QSFP/QSFP+ ports and high-performance low-jitter Silicon
Labs programmable clock (default = 156.25Mhz). The I2C interface between
the oscillator and FPGA allows direct control of the QSFP/QSFP+ ports for
wide range of different frequencies. The QSFP/QSFP+ ports are directly
connected to four multi-gigabit serial transceivers of Vita 57
compliant carrier FPGA boards.
►x2 QSFP+ (2x40G) Connectors -
or x8 SFP+ (8x10G) ports using the QSFP+ to SFP+ breakout
►x1 programmable oscillator with start up frequency of 156.25MHz
( other frequencies are supported through the I2C and the host FPGA)
differential clock SMA port
(direct interface to the FPGA)