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100Gig Ethernet MAC & PCS IP Core - ASIC & FPGA


The 100Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethernet switching applications. As shown in the figure below, the 100Gbps Ethernet IP includes:

·         100Gbps MAC core

·         100Gbps (100GBase-R) PCS core with support for CAUI-4 (-C4 option) and CAUI-10 (-C10 option) interfaces

·         Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs

·         Statistics counter block (for RMON and MIB)

·         MDIO and I2C cores for optical module status and cont

A complete reference design using a synthesizable L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference design’s hardware elements through a UART interface (PCIe option is also available). A basic Linux PCIe driver/API is also provided for memory mapped read/write access to the internal registers.

MAC and PCS cores are designed with 320-bit data path operating at 312.5MHz. 

As the transceiver wrapper is included with the Ethernet IP solution, the line side directly connects the 10.3125Gbps (for CAUI-10 interface) or 25.78125Gbps (for CAUI-4 interface) FPGA transceivers to various optical modules including CFP, CFP2, CFP4, CXP and QSFP28. 

Ethernet IP solution implements two user (application) side interfaces. The register configuration and control port is a 32-bit AXI4-Lite interface. A 512-bit non-segmented AXI-4 streaming bus at 312.5MHz is used to interface with the MAC block.  Additionally, an interface wrapper is provided to support segmented interface operation at lower clock speeds.

100Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels. 

Features Overview 

MAC Core Features

      Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.

      Implements 802.3bd specification with ability to generate and recognize PFC pause frames

      Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.

      Implements a 320-bit CGMII interface operating at 312.5 MHz for 100G EMAC

      Implements Deficit Idle Count (DIC) mechanism to ensure maximum possible throughput at the transmit interface.

      Implements logic for padding of frames on the transmit path if the size of frame is less than 64 bytes.

      Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention. Non PFC mode only.

      Pause frame generation additionally controllable by user application offering flexible traffic flow control.

      Support for VLAN tagged frames according to IEEE 802.1Q.

      Support any type of Ethernet Frames such as SNAP / LLC, Ethernet II/DIX or IP traffic.

      Discards frames with mismatching destination address on receive (Except Broadcast and Multicast frames).

      Supports programmable promiscuous mode to omit MAC destination address checking on receive EMAC.

      Optional multicast address filtering with 64-bit HASH Filtering table providing imperfect filtering to reduce load on higher layers.

      CRC-32 generation and checking at high speed using an efficient pipelined CRC calculation algorithm.

      Implements logic for optional padding removal on RX path for NIC applications or forwarding of unmodified data to the user interface.

      Discards runt frames (less than 64 Byte) at the core’s reconciliation sublayer.

      Implements logic for optional forwarding of the CRC field to user application interface.

      Implements logic for optional forwarding of received pause frames to the user application interface.

      Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).

      Status signals available with each Frame on the user interface providing information such as frame length, VLAN frame type indication and error information.

      Implements programmable internal CGMII Loop-back.

      Implements statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames.

      Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments.

      Implements a streaming user application interface. The application interface is designed as a 512-bit non-segmented (start of a new frame on next 512-bit word) interface operating at 312.5MHz.

      An interface wrapper is provided for applications that implement a segmented (start of new frame within same 512-bit word) bus. In segmented mode, the 512-bit bus operates at @ 225MHz for 100Gbps.

      Implements memory-mapped host controller interface for accessing the core’s register file.

PCS Core Features (Common)

      Implements 100GBase-R PCS core compliant with IEEE 802.3ba Specifications.

      Implements a 320-bit CGMII interface operating at 312.5MHz for 100G Ethernet.

      Implements 64b/66b encoding/decoding for transmit and receive PCS.

      Implements 100G scrambling/descrambling using 802.3ba specified polynomial 1 + x39 + x58

      Implements Multi-Lane Distribution (MLD) across 20 Virtual Lanes (VLs)

      Implements periodic insertion of Alignment Marker (AM) on the transmit path and deletion on the receive path

      Implements 66-bit block synchronization and Alignment Marker Lock machines as specified in 802.3ba specifications.

      Implements skew compensation logic in order to realign all the virtual lanes and reassemble an aggregate 100G stream (with all 64b/66b blocks in the correct order)

      Implements lane reordering to support reception of any virtual lane (VL) on any physical lane (PL).

      Implements BIP-8 insertion/checking per Virtual Lane on transmit/receive respectively.

      Implements Inter Packet Gap (IPG) Insertion/Deletion for Alignment marker and clock compensation while maintaining a minimum of 1 byte IPG.

      Implements programmable internal CGMII loop-back which directs traffic received from core's receive path back to transmit PCS.

      Implements Bit Error Rate (BER) monitor for monitoring excessive error ratio. In addition, the core implements various status and statistics required by the IEEE 802.3ba  such as block synchronization status, AM lock status, lane deskew and lane reordering status and BIP-8 error counters per virtual lane.

PCS Core Features (CAUI-4 Option)

      Implements gear-box logic to convert 20 VLs of 66-bit blocks to 10 PLs of 40-bit data for line side CAUI-10 interface. The 40-bit interface operates at the transceiver reference clock of 25.78125MHz.

      Transceiver Wrappers for Xilinx Series-7 GTZ transceivers

PCS Core Features (CAUI-10 Option)

      Implements gear-box logic to convert 20 VLs of 66-bit blocks to 4 PLs of 160-bit data for line side CAUI-4 interface. The 160-bit interface operates at the transceiver reference clock of 161.1328125MHz.

      Transceiver Wrappers for Xilinx Series-7 GTX/GTH transceivers, Xilinx Virtex-6 GTH transceivers and Altera Startix-IV ALT-GXB transceivers

Licensing and Maintenance

-NO yearly maintenance fees for upgrades and bug fixes

-Basic core licensing for a single vendor (either Xilinx or Altera) compiled (synthesized Netlist) binary 
- Other licensing options include: Vendor and device family agnostic source code (Verilog) license

Resource Utilization

The core utilization summary for the 100G Ethernet solution is given in following tables. The Ethernet solution has been fully verified on different hardware platforms for both Altera and Xilinx FPGAs.

100G Ethernet - Resource Usage for Xilinx Devices


User Interface        (AXI4-ST)

Priority Flow Control (PFC)

PCS Type

Slice LUTS

Slice Registers



(-2C Speed)






18K = 4; 36K = 74





18K = 4; 36K = 74





18K = 4; 36K = 74





18K = 4; 36K = 74


(-2C Speed)






18K = 4; 36K = 74





18K = 4; 36K = 74

Note: Register based RMON statistics block adds additional 1948 LUTs and 1807 registers.

100G Ethernet - Resource Usage for Altera Devices (CAUI-10 Only)


User Interface (AXI4-ST)

Priority Flow Control (PFC)



Memory M9K


(-C2 Speed)










Note: Register based RMON statistics block adds additional 2000 LUTs and 1800 registers.


·         Compiled synthesizable binaries or encrypted RTL for the MAC and PCS cores

·         Source code RTL (Verilog) for MDIO, RMON and Register-File blocks  

·         Self checking behavioral models and test benches for simulation

·         Constraint files and synthesis scripts for design compilation

·         A complete PCIe/UART host interface based reference design with:

o    Top level wrapper (source files, Verilog)

o    Source files (Verilog) for the PICe application layer

o    Binaries for the L2 packet generator and checker

o    PCIe driver/API (source files, C) for Linux

o    UART and command interpreter blocks with the optional UART host interface 

o    GUI application (Linux only for PCIe, Linux and Windows for UART) for interfacing to the reference design

·         Design guide(s) and user manuals

GUI interface for the Reference Desig

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