XMAC: 10 Gigabit Ethernet MAC IP Core

Overview:
XMAC is a highly configurable 10Gigabit Ethernet MAC core for use in multi gigabit chip designs. The core architecture is carefully tailored for high throughput, low latency, high performance, and small silicon footprint.

The hardware and software configurable features allow the core to be used in switching, routing, uplinks, line cards, NICs, server adapters and other SOC applications. The core's simple, configurable and layered architecture is independent of application logic, PHY designs, implementation tools and, most importantly, target technologies. The XMAC is a cost effective, end-to-end system validated solution that allows the licensees to easily migrate to FPGA, Gate array and Standard cell technologies optimally. The XMAC provides XGMII interface to the line side and a flexible backend interface to the user logic on the system side.

The XMAC core has successfully completed the compliance testing at the 10Gigabit Ethernet Consortium, University of New Hampshire InterOperability Lab.

Main Features: 

• 10 Gigabit Ethernet Media Access Controller compliant to IEEE 802.3ae-2002 specification
• Supports full duplex flow control - compliant to IEEE 802.3x
• Supports VLAN - compliant to IEEE 802.3ac, IEEE 802.1Q
• Supports OC-192c PHY devices in programmable WAN mode
• XGMII interface on line side
• 64-bit wide, point-to-point Data Transfer Interface (DTI) on system side
• Store-and-forward and cut-through modes of operation
• Jumbo and short frame support
• Optional FIFO Interface on system side
• 32-bit Peripheral Bus Interface on host side
• Management counters for RMON, SNMP, and 802.3ae
• Flexible address filtering options: UC, MC, BC and promiscuous
• Configurable and Programmable receive filtering options for Pattern Match, Exact Address Match, MC and VLAN hash.
• UNH compliance testing adhering to IEEE 802.3ae specification
  

Configurable Options Receive and Transmit FIFO depths Size of the MC and VLAN hash tables Inclusion of number of wire speed pattern match filters Inclusion of PHY management (STA) logic and RMONstatistics counters. Mode of data transfer: Cut-through/Store-and-forward Inter packet gap (IPG) for traffic shaping CRC append/modify enable for transmit packets WAN Mode data rate control enable Effective data rate control through IPG dithering Programmable Broadcast storm control thresholds Cut Thru Thresholds for transmit and receive FIFO PAUSE time for flow control frame	Design Attributes Fully synchronous, technology–independent design Software controlled block resets and enables 64-bit wide internal data path 156.25 MHz clock for most of the MAC logic Highly modular design: partitioned by function, timing, and testability
Product Package Parameterized RTL Code Automated and parameterized test bench Test cases Synthesis environment/scripts	Documentation Design guide. Verification guide Synthesis guide User guide.
Status: Gold [system validated] Availability: Available Language: Verilog HDL Synthesis: Ambit/Synopsys/Synplify Simulation: Cadance's Verilog-XL/NC Verilog Technology: 0.18u or better Price:

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