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25Gig Ethernet MAC & PCS IP Core - Xilinx/Altera FPGAs & ASIC/SOC

The 25Gbps 64-bit Ethernet IP solution offers a fully integrated IEEE P802.3by compliant package for NIC (Network Interface Card) and Ethernet switching applications. As shown in the figure below, the 25Gbps Ethernet IP includes:

25Gbps MAC core with AXI-4 Streaming or Avalon Streaming user interface
25GBase-R PCS with 25G 25GAUI interface for direct SFP28 module attachment
Technology dependent transceiver wrapper for Altera and/or Xilinx FPGAs
Statistics counter block (for RMON and MIB)
MDIO and I2C cores for external module and optical module status/control


A complete Reference Design using a L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference designís hardware elements through a UART interface (a PCIe option is also available). An application (with optional basic Linux PCIe driver/API) is also provided for memory mapped read/write access to the internal registers.

MAC core is designed with 64-bit data path operating at 390.625MHz to take advantage of high performance fabrics of the 28nm, 20nm and 16nm FPGAs.

As the PCS and transceiver wrapper is included with the Ethernet IP solution, the line side directly connects the 25.78125Gbps FPGA transceiver to the optical module (SFP28-SR).

Ethernet IP solution implements two user (application) side interfaces. The register configuration and control port is a 32-bit AXI4-Lite or Avalon-MM interface and 64- bit @390.625MHz AXI-4 Streaming or Avalon Streaming bus to interface with the MAC block.

25Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels.

Features Overview

MAC Core Features

Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.
Implements 802.3bd specification with ability to generate and recognize PFC pause frames.
Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.
User interface option for the MAC data path: AXI-4 or Avalon streaming with 64-bit data path at 390.625MHz
PCS layer 25GMII interface implemented as 64-bit (single data rate) SDR interface at 390.625MHz
Deficit Idle Count (DIC) mechanism to ensure data rates of 25Gbps at the transmit interface.
Optional padding of frames if the size of frame is less than 64 bytes.
Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention. Non PFC Mode only.
Pause frame generation additionally controllable by user application offering flexible traffic flow control.
Support for VLAN tagged frames according to IEEE 802.1Q.
Support any type of Ethernet Frames such as SNAP / LLC, Ethernet II/DIX or IP traffic.
Discards frames with mismatching destination address on receive (except Broadcast and Multicast frames).
Programmable Promiscuous mode support to omit MAC destination address checking on receive path.
Optional multicast address filtering with 64-bit Hash Filtering table providing imperfect filtering to reduce load on higher layers.
High speed CRC-32 generation and checking.
Optional prevention of CRC appending in frame data by MAC to allow CRC to be pre-embedded in frame data by user application.
Optional insertion of error control character in transmitted frame data.
Optional forwarding of the CRC field to user application interface.
Programmable frame maximum length providing support for any standard or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).
Status signals available with each Frame on the user interface providing information such as frame length, VLAN frame type indication and error information.
Optional padding termination on RX path for NIC applications or forwarding of unmodified data to the user interface.
Optional internal 25GMII Loop-back.
Statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames.
Altera Avalon or Xilinx AXI4 interface compliant user (FIFO) interface.
Transmit and Receive FIFOs with configurable depths having a default depth of 1KB (128 64-bit words) each, according to user interface bus width.
Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments.

PCS Core Features

Implements 25GBase-R PCS core compliant with IEEE P802.3by Specifications.
Implements a 64-bit 25GMII interface to operate at 390.625MHz for 25G Ethernet.
Implements 64b/66b encoding/decoding for transmit and receive PCS using 802.3-2015 specified control codes.
Implements 25G scrambling/descrambling using P802.3by specified polynomial 1 + x39 + x58.
Implements 66-bit block synchronization state machine as specified in P802.3by specifications.
Implements Inter Packet Gap (IPG) insertion/deletion for clock compensation while maintaining a minimum of 5 bytes IPG.
Implements gear-box logic for Xilinx to convert 66-bit blocks to 160-bit for line side. The 160-bit interface operates at the transceiver reference clock of 161.1328125MHz.
Implements gear-box logic for Altera to convert 66-bit blocks to 128-bit for line side. The 128-bit interface operates at the transceiver reference clock of 201.416015625MHz.
Implements Bit Error Rate (BER) monitor for monitoring excessive error ratio. In addition, the core implements various status and statistics required by the IEEE P802.3by such as block synchronization status and test mode error counter.
Implements optional 25GMII remote loopback to loopback data received from Rx PCS back to Tx PCS.

Licensing and Maintenance

NO yearly maintenance fees for upgrades and bug fixes
Basic core licensing for a single vendor (either Xilinx or Altera) compiled (synthesized Netlist) binary
Vendor and device family agnostic source code (Verilog) license


Compiled synthesizable binaries or encrypted RTL for the MAC core
Source code RTL (Verilog) for I2C, MDIO, RMON and Register-File blocks
Self-checking behavioral models and test benches for simulation
Constraint files and synthesis scripts for design compilation
A complete UART/PCIe host interface based reference design with:
   o Top level wrapper (source files, Verilog) for user specific customizations
   o Source files (Verilog) for the PCIe application layer
   o Binaries for a basic L2 packet generator and checker
   o UART and command interpreter blocks with the optional UART host interface
   o PCIe driver/API (source files, C) for Linux with the optional PCIe interface
   o GUI application (Linux only for PCIe, Linux and Windows for UART) for interfacing to the reference design

Design guides and user manuals

Resource Utilization

Ported/Validated Modules List

1. HiTech Global HTG-828 and HTG-9100 platforms: Xilinx Virtex UltraScale FPGA with 25Gbps transceivers, Optical module with CFP4 and QSFP28 interfaces. Parallel MTP/MTO to quad SFP+ breakout cable used for 25Gbps interface.

2. HiTech Global HTG-728 platform; Xilinx Virtex-7 H580T FPGA with 25Gbps transceivers, Optical module with CFP2 and CFP4 interfaces. Parallel MTP/MTO to quad SFP+ breakout cable used for 25Gbps interface.

3.HiTech Global HTG-830 platform; Xilinx Virtex UltraScale FPGA with 25Gbps transceivers, optical modules with SFP28, and QSFP28