Dual Mode 40/100Gig Ethernet MAC & PCS IP Core - Xilinx/Altera FPGAs & ASIC/SOC
The dual-mode 100Gbps/40Gbps Ethernet IP solution offers a fully integrated IEEE802.3ba compliant package for NIC (Network Interface Card) and Ethernet switching applications. As shown in figure, the 100G/40G Ethernet IP includes:
∑ 100Gbps/40Gbps dual-mode MAC core
∑ 100Gbps/40Gbps dual-mode PCS core
∑ Technology dependent transceiver wrapper
∑ Statistics counter block (for RMON and MIB)
∑ MDIO and I2C cores for optical module status and control
A complete reference design using a synthesizable L2 (MAC level) packet generator/checker is also included to facilitate quick integration of the Ethernet IP in a user design. A GUI application interacts with the reference designís hardware elements through a UART interface (PCIe option is also available). A basic Linux PCIe driver/API is also provided for memory mapped read/write access to the internal registers.
MAC and PCS cores are designed with 320-bit data path operating at 312.5MHz.
As the transceiver wrapper is included with the Ethernet IP solution, the line side directly connects the 10.3125Gbps FPGA transceivers to the optical modules like QSFP+ (40Gbps only), CFP, CXP, 300Pin MSA, etc).
Ethernet IP solution implements two user (application) side interfaces. The register access port can either be a 32-bit AXI4 interface or a 32-bit Avalon-MM interface. IP solution provides a highly flexible 100Gbps traffic port interface options. Depending upon the application layer, user can select an AXI-4 streaming bus or an Avalon Streaming bus to interface with the MAC block. MAC interface bus is a 512-bit non-segmented bus that operates at 312.5MHz for 100Gbps mode and 125MHz for the 40Gbps mode. An interface wrapper is provided to support segmented operation at lower clock speeds.100Gbps Ethernet IP supports advanced features like per-priority pause frames (compliant with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE) applications like data center bridging that employ IEEE 802.1Qbb Priority Flow Control (PFC) to pause traffic based on the priority levels.
● Enables the run-time selection of 100Gbps or 40Gbps Ethernet operation with a single FPGA image
MAC Core Features
● Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.
● Implements 802.3bd specification with ability to generate and recognize PFC pause frames
● Implements a 320-bit CGMII/XLGMII interface operating at 312.5 MHz for 100Gbps mode or 125 MHz for 40Gbps mode
● Implements Deficit Idle Count (DIC) mechanism to ensure maximum possible throughput at the transmit interface
● Implements logic for padding of frames on the transmit path if the size of frame is less than 64 bytes
● Implements fully automated XON and XOFF Pause Frame (802.3 Annex 31A) generation and termination providing flow control without user application intervention
● Pause frame generation additionally controllable by user application offering flexible traffic flow control
● Support for VLAN tagged frames according to IEEE 802.1Q
● Support any type of Ethernet Frames such as SNAP/ LLC, Ethernet II/DIX or IP traffic
● Discards frames with mismatching destination address on receive (Except Broadcast and Multicast frames)
● Programmable Promiscuous mode to omit MAC destination address checking on receive EMAC
● Optional multicast address filtering with 64-bit HASH Filtering table providing imperfect filtering to reduce load on higher layers
● CRC-32 generation and checking at high speed using an efficient pipelined CRC calculation algorithm
● Implements logic for optional padding removal on RX path for NIC applications or forwarding of unmodified data to the user interface
● Discards runt frames (less than 64 Byte) at the coreís reconciliation sublayer
● Implements logic for optional forwarding of the CRC field to user application interface
Implements logic for
optional forwarding of received pause frames to the user application
● Implements programmable internal XLGMII/CGMII Loop-back
● Implements statistics indicators for frame traffic as well as errors (alignment, CRC, length) and pause frames
● Implements statistics and event signals providing support for 802.3 basic and mandatory managed objects as well as IETF Management Information Database (MIB) package (RFC 2665) and Remote Network Monitoring (RMON) required in SNMP environments
● Implements a streaming user application interface. The application interface is designed as a 512-bit non-segmented (start of a new frame on next 512-bit word) bus operating at 312.5MHz for 100Gbps mode and at 125MHz for 40Gbps mode.
● An interface wrapper is provided for applications that implement a segmented (start of new frame within same 512-bit word) bus. In segmented mode, the 512-bit bus operates at @ 225MHz for 100Gbps.
● Implements memory-mapped host controller interface for accessing the coreís register file
PCS Core Features
● Implements 40G/100GBase-R PCS core compliant with IEEE 802.3ba Specifications
● Implements a 320-bit CGMII/XLGMII interface operating at 125MHz/312.5MHz for 40G/100G Ethernet
● Implements 64b/66b encoding/decoding for transmit and receive PCS
● Implements 40G/100G scrambling/descrambling using 802.3ba specified polynomial 1 + x39 + x58
● Implements Multi-Lane Distribution (MLD) across 20 or 4 Virtual Lanes (VLs) for 100Gbps or 40Gbps operations respectively
● Implements periodic insertion of Alignment Marker (AM) on the transmit path and deletion on the receive path
● Implements 66-bit block synchronization and Alignment Marker Lock machines as specified in 802.3ba specifications
● Implements skew compensation logic in order to realign all the virtual lanes and reassemble an aggregate 40G/100G stream (with all 64b/66b blocks in the correct order)
● Implements lane reordering to support reception of any virtual lane on any physical lane.
● Implements BIP-8 insertion/checking per Virtual Lane on transmit/receive respectively.
● Implements Inter Packet Gap (IPG) Insertion/Deletion for Alignment marker compensation while maintaining a minimum of 1 byte IPG.
● Implements gear-box logic to convert 66-bit blocks to 20/40-bit for 40/100G PCS. The 20/40-bit interface operate at the transceiver reference clock.
● Implements programmable internal CGMII/XLGMII loop-back which directs traffic received from core's receive path back to transmit PCS.
Implements Bit Error Rate
(BER) monitor for monitoring excessive error ratio. In addition, the
core implements various status and statistics required by the IEEE
802.3ba such as block synchronization status, AM lock status, lane
deskew and lane reordering status and BIP-8 error counters per virtual
Licensing and Maintenance
The 40G/100G Ethernet solution is currently supported on Xilinx and Altera FPGA devices as well as ASIC / SOC implementations.
∑ Compiled synthesizable binaries or encrypted RTL for the MAC and PCS cores
∑ Source code RTL (Verilog) for I2C, MDIO, RMON and Register-File blocks
∑ Self checking behavioral models and test benches for simulation
∑ Constraint files and synthesis scripts for design compilation
∑ A complete PCIe/UART host interface based reference design with:
o Top level wrapper (source files, Verilog) for user specific customizations
o Source files (Verilog) for the PIC Express application layer
o Binaries for the L2 packet generator and checker
o PCIe driver/API (source files, C) for Linux
o UART and command interpreter blocks with the optional UART host interface
o GUI application (Linux only for PCIe, Linux and Windows for UART) for interfacing to the reference design
∑ Design guide(s) and user manuals
∑ USA based technical support by developers