Block Descirption:
Opcode Decoder
Performs an instruction opcode decoding
and the control functions for all other
blocks.
Control Unit
Performs the core synchronization and
data flow control. This module manages
execution of all instructions. The
Control Unit also manages HALT input pin
events.
Bus Control
Program Memory, Data Memory interface
controls access into the program and
data memories. It contains Program
Counter (PC), Stack Pointer (SP)
register, and related logic.
Interrupt Controller
Interrupt Controller – Interrupt Control
module is responsible for the interrupt
manage system for the external &
internal interrupts and exceptions
processing. It manages auto-vectored
interrupt cycles, priority resolving and
correct vector numbers creation.
ALU
Arithmetic Logic Unit performs the
arithmetic and logic operations during
execution of an instruction. It contains
accumulator (A, B), Condition Code
Register (CCREG), Index register X and
related logic like arithmetic unit,
logic unit, multiplier and divider.
DoCDTM Debugger
iIt is a real-time hardware debugger
provides debugging capability of a whole
SoC system. In contrast to other on-chip
debuggers DoCD™ provides non-intrusive
debugging of running application. It can
halt, run, step into or skip an
instruction, read/write any contents of
microcontroller including all registers,
internal, external, program memories,
all SFRs including user defined
peripherals. Hardware breakpoints can be
set and controlled on program memory,
internal and external data memories, as
well as on SFRs. Hardware breakpoint is
executed if any write/read occurred at
particular address with certain data
pattern or without pattern. The DoCDTM
system includes three-wire interface and
complete set of tools to communicate and
work with core in real time debugging.
It is built as scalable unit and some
features can be turned off to save
silicon and reduce power consumption. A
special care on power consumption has
been taken, and when debugger is not
used it is automatically switched in
power save mode. Finally whole debugger
is turned off when debug option is no
longer used. The separate CLKDOCD clock
line allow the debugger to operate while
the CPU is in STOP mode and the major
clock line CLK is stopped.
Implementation Results:
| Implementation | Speed Grade | Utilized Area [LC] | Frequency [MHz] |
| CYCLONE | -6 | 1430 | 55 |
| CYCLONE II | -6 | 1429 | 49 |
| CYCLONE III | -6 | 1429 | 64 |
| STRATIX | -5 | 1433 | 61 |
| STRATIX II | -3 | 1001 | 102 |
| STRATIX III | -2 | 993 | 118 |
| STRATIX GX | -5 | 1433 | 64 |
| STRATIX II GX | -3 | 992 | 99 |
Xilinx and Lattice
FPGAs are also supported.
