DoCD^TM
DoCD Debug Unit – it’s a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.
The separate DoCD clock line allow debugger to operate while the SLEEP mode (major clock line CLK is stopped).

Watchdog Timer
The Watchdog Timer consist of free running timer CLK/2¹³, plus control logic. The Watchdog Timer can be enabled by software by writing '1' to the WDOG Bit in MISC ($0C) register. Once enabled the WDT timer cannot be disabled by software. In addition the WDOG bit acts as a reset mechanism for the WDT Timer. Writing '1' to the WDOG Bit clears WDT counter and inhibits Watchdog timeout.

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index registers (H:X), and related logic such as arithmetic unit, logic unit, multiplier and divider.

SPI
It’s a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.

SCI
The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem.

BREAK MODULE
The break module (BRK) can generate a break interrupt that stops normal program flow at a defined address to enter a background program.

Interrupt Controller
External Interrupt Controller

COP
The Computer operating properly - COP - module contains a free-running counter that generates a reset if allowed to overflow. The COP module helps software recover from runaway code. Prevent a COP reset by clearing the COP counter periodically. The COP module can be disabled via a mask option, the COPD bit in mask option register A (MORA).

I/O Ports
All D68HC08 I/O ports are programmable, and can operate as inputs or outputs.

PIT
Programmable Interrupt Timer - PIT - is the 16-bit counter that can operate as a free-running counter or a modulo up-counter. The counter provides the timing reference for the interrupt. The PIT counter modulo registers, PMODH:PMODL, control the modulo value of the counter. Software can read counter value at any time without affecting the counting sequence.

TIMA
Timer Interface Module A. The TIMA is a four channel timer, thet provides a timing reference with input capture, output compare and pulse-width modulation functions.

TIMB
Timer Interface Module B. The TIMB is a four channel timer, thet provides a timing reference with input capture, output compare and pulse-width modulation functions.

CPU
Central Processing Unit - CPU - contains instruction decoder, manager program execution and interrupts handling. Contains control and status registers.