ATA-7 Device IP Core
Main Features:
- PIO modes 0-4
- IORDY signaling for PIO cycle extension
- Multi-word DMA modes 0-2
- Ultra DMA modes 0-6
- Programmable timings for PIO and DMA modes
- Support for Ultra DMA pause and termination
- Standard slave Wishbone interface to microprocessor/microcontroller
- Interrupt generator for IRQ driven software driver implementation
- Automatic handling of BSY and DRQ bits
- DMA engine and master Wishbone interface for data transfer
- Small register FIFOs for transmit and receive data
- Acts as a single, master ATA/ATAPI device on ATA cable
- 66MHz clock for UDMA133 (mode 6) operation
Architecture:
Verification:
ATA device IP core has been thoroughly exercised. A self checking
Verilog test bench with a test suite is supplied with the core. Test
suit includes all major modes of core operation : configuration, PIO
transfers, multi-word DMA, Ultra DMA with examples of device and host
terminating/pausing data-in/ data-out bursts.
ATA device IP core demo is available, demonstrating core usage in Xilinx
MicroBlaze base SOC implemented on Xilinx Virtex V4 LX25LC. Demo is a
fully functional ATA7 hard drive that can be connected to PC IDE
controller.
Size & Speed:
Sample Synthesis results for ATA-7 Device IP Core. The goal was smallest and fastest implementation.
| Technology | Gate Count | Operating Frequency |
| UMC 0.18 um | 5.2K Gates | > 66MHz |
| Xilinx Virtex 5 (XC5VLX30T-1) | 438 Slices | > 130MHz |
| Xilinx Virtex 4 (XC4VFX20-10) | 943 Slices | >100 MHz |
| Xilinx Spartan 3E (XC3S1200E-4) | 1,102 Slices | > 66MHz |
Price:
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HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel:+ 1 408 781-8043
Fax: + 1 408
268-4173
Email:
info@hitechglobal.com