ATA-7 Host Controller IP Core

A ATA-7 compliant host controller core to interface to ATA devices like hard-disks, CD and DVD drives. This core is targeted for SOC implementations in ASIC and FPGA.

Main Features: 

• PIO modes 0-4
• Multi-word DMA modes 0-2
• Ultra DMA modes 0-6
• Programmable timings for PIO and DMA modes
• Support for Ultra DMA pause and termination
• Standard slave Wishbone interface to microprocessor/microcontroller Architecture
• Interrupt generator for IRQ driven software driver implementation
• Transparent (pass through) access from processor interface to device task registers
• DMA engine and master Wishbone interface for data transfer
• Small register FIFOs for transmit and receive data
• 66MHz clock for UDMA133 (mode 6) operation

Additional functions or customization can be easily done per customers request.
ATA host controller core is written in Verilog.

Verification:
ATA host core has been thoroughly exercised. A self checking Verilog test bench with a test suite is supplied with the core. The test suit includes all major modes of core operation : configuration, PIO transfers, multi-word DMA, Ultra DMA with examples of device and host terminating/pausing datain/data-out bursts.

An ATA host core reference design is also available, demonstrating core usage in Xilinx MicroBlaze based SOC implemented on Xilinx Virtex V4LX25LC. Demo is a fully functional ATA7 hard drive controller that can be connected to standard hard disks, demonstrating basic file handling.

AHB, OCP , OPB, AVALON, WISHBONE, and CUSTOM buses are supported.

Size & Speed:
Sample Synthesis results for ATA-7 Host IP Core. The goal was smallest and fastest implementation.

Price:

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