Configurable CAN 2.0 (Controller Area Network) Controller IP Core

General Description:

The CAN (Controller Area Network) is a stand-alone controller for the Controller Area Network widely used in automotive and industrial applications. CAN conforms to Bosch CAN 2.0B specification (2.0B Active). Core has simple CPU interface (8/16/32 bit configurable data width) with little or big endian addressing scheme. CAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The CAN is described at RTL level allowing target use in FPGA or ASIC technologies.

Key Features:

Conforms to Bosch CAN 2.0B Active
8/16/32-bit CPU slave interface with little or big Endianess
Simple interface allows easy connection to CPU
Based upon SJA1000 in PeliCAN mode
Data rate up to 1 Mbps
Hardware message filtering (dual/single filter)
64 byte receive FIFO
One transmit buffer
No overload frames are generated
Normal & Listen Only Mode
Single Shot transmission
Ability to abort transmission
Readable error counters
Last Error Code
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Automotive, industrial
Embedded communication systems

Units

RX RAM Interface
Interface to external dual port memory used by the DCAN core to store received frames.

Receive FIFO
Receive FIFO controller

ACF Acceptance Filter
Decides whether incoming messages are accepted or not based upon filter registers settings.

BRP Baud Rate Prescaler
Defines the length of time quantum.

BSP Bit Stream Processor
Translates messages into frames and vice versa.

BTL Bit Timing Logic
Processes the bit time, calculates position of the sample point and performs synchronization.

EML Error Management Logic
EML is responsible for fault confinement handling.

IML Interface Management Logic
Interprets commands from the CPU, provides interrupt and status indication.

TX RAM Interface
Interface to external dual port memory used by the DCAN core to store transmitted frames.

Performance:

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN III E	-7	1049	62
SPARTAN-III	-5	1033	84
SPARTAN-IIE	-7	1055	60
SPARTAN-II	-6	1057	58
VIRTEX	-6	1058	51
VIRTEX-E	-8	1057	72
VIRTEX-II	-6	1032	103
VIRTEX-II pro	-7	1034	120
VIRTEX-IV	-11	1032	120

8-bit CAN implementation results for XILINX devices.

Implementation	Speed grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	1956	66
ACEX1K	-1	1956	66
APEX20K	-1	1956	66
APEX20KE	-1	1956	83
APEX20KC	-7	1956	94
APEX II	-5	1956	108
CYCLONE	-6	1956	123
CYCLONE II	-6	1899	137
STRATIX	-5	1956	130
STRATIX II	-3	1529	188
STRATIX GX	-5	1956	131

8-bit CAN implementation results in ALTERA devices.

Licensing:

Comprehensible and clearly defined licensing methods
without royalty fees make using of IP Core easy and simple..

Single Design license allows use IP Core in single
FPGA bitstream and ASIC implementation.
Unlimited Designs, One Year licenses allow use
IP Core in unlimited number of FPGA bit-streams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months.
Royalty: The CAN Protocol is protected by BOSCH patents. Royalties are applicable and payable to BOSCH for commercial production of systems using the CAN IP core in FPGA and/or ASIC.

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Upgrade from:
- HDL Source to Netlist
- Single Design to Unlimited Designs

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

www.HiTechGlobal.com

HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel:+ 1 408 781-8043
Fax: + 1 408 268-4173
Email: info@hitechglobal.com

Units

Performance:

Licensing:

Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simple..

Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Upgrade from: - HDL Source to Netlist - Single Design to Unlimited Designs

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using of IP Core easy and simple..

Single Design license allows use IP Core in single
FPGA bitstream and ASIC implementation.

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Upgrade from:
- HDL Source to Netlist
- Single Design to Unlimited Designs