Configurable SPDIF-AES/EBU Transmitter IP Core
Overview:
The CWda15 Configurable SPDIF-AES/EBU Transmitter is a digital
audio transmitter IP core supporting the SPDIF IEC60958, AES/EBU and
AES3 standard and also the IEC61937 and SMPTE 337M for non-PCM audio.
When transmitting PCM audio, the user must ensure the availability of
data in the FIFO. If the FIFO gets empty, silencing SPDIF frames marked
as invalid sent are until the arrival of new audio data. When
transmitting Non-PCM bursts, the CWda15 will optionally fill the SPDIF
sub-frames with zeros until the next burst, if the repetition periods
for the data burst and the pause burst are provided. When the FIFO is
empty, the CWda15 sends bit stuffing and periodic NULL Data Bursts
according to the Non-PCM IEC61937 standard. The Modular structure of
CWda15 allows enhanced performance for specific applications by using
(not using) the optional Addon- Modules (AOM).
Functional description:
FIFO: this is a circular, asynchronous, first in first out
RAM used to save audio data (PCM /non-PCM). It contains a register to
indicate the number of words present in the FIFO at each moment.
Attempts to write when it is full will assert low the write signal.
Register File: contains information concerning the
state of the CWda15 IP core, and concerning the audio stream being sent.
It also contains the FIFO information regarding the number of words
currently in of the FIFO, its maximum capacity, and the configurable
register Lower FIFO Limit.
User & Channel Status Bits Buffers: the user and channel status
bits can be saved in internal buffers that are organized in 192-bit
blocks subdivided into 24 bytes. These bytes can be programmed by
addressing them from the Control CW-link interface.
Optional Buffers: When the pre-synthesis parameter
use_dual_buffering is set, the user and status bits are read from these
optional buffers. After the complete relay of an SPDIF block, the bits
in the user-accessible User & Status Bits Buffers (mentioned before) are
copied into these buffers to be used while transmitting the next SPDIF
block. This allows the user the time of one entire SPDIF block to write
the
new data into the User & Status Bits Buffers (1 ms at 96kHz).
SPDIF Encoder: retrieves audio data from the FIFO
and according to the control bits in the Configuration Register builds
the SPDIF frame, selecting the appropriate preamble and making the data
available when needed. It also calculates the parity bit, signals the
start of a frame and sets the frame number.
Stream Packer: Manage the non-PCM stream. It composes the data
and pause bursts according the current configurations generating any
necessary stuffing. If incoherent data is read from the FIFO the stream
packer filters those data sending bit stuffing until a new valid data
burst occur.
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Key Features:
Applications:
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Benefits:
Deliverables: • Detailed datasheet and user documentation for system integration. Part Number:
CWda15
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Implementation Results:
Implementation results for the CWda15 (BS + CW-Link)
Implementation results for the CWda15 (All AOM) Other Digital Audio IP Cores:
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