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I2S - Configurable
Digital Audio Serial
Input
IP Core
Overview:
The CWda16 IP core is a configurable
stereo audio interface component designed to input a serial digital
audio stream. The CWda16 supports the well known I2S interface
format originally developed by Philips and also the Left-Justified or
Right-Justified serial audio formats. The CWda16 can be configured at
runtime to support two (16, 20, 24 or 32 bit) audio channels read from
two different addresses in an interleaved manner, or two 16-bit audio
channels read in parallel from the same register.
Functional Description:
Configurable Serial Decoder:
Can be configured to convert the various kinds of incoming serial
audio streams in the parallel CW-Link interface.
FIFO:
This is a circular asynchronous first in first out RAM used to save
audio samples. Its contains a register to indicate the number of words
present in the FIFO at each moment. Attempts to read when it is empty
will assert low the read acknowledge signal, and attempts to write when
it is full will be ignored, causing the newly arrived samples to be
dropped until there is again space in the FIFO. The asynchronous FIFO
can be preceded by a synchronous FIFO with configurable depth.
Register File:
Contains the configuration and information registers regarding the
number of words currently in the FIFO, its maximum capacity, the
programmable Upper-FIFO-Limit register, etc.
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Key Features:
- Configurable input format: I2S, Left Justified or
Right justified (chosen at runtime)
- Configurable sample FIFO depth (at pre-synthesis
time)
- Supports user configurable sample width (at runtime)
- Reports number of samples in FIFO
- Reports FIFO empty, full, almost empty and almost
full condition
- Runtime Configurable Upper-FIFO-Limit; a request is
activated when this limit is exceeded
- Supports up to 32 bits per sample
- Supports all commonly used sample rates including 32,
44.1, 48, 96, 192 and 384 kHz
- Runtime Configurable read method. Serial sample read
(Left and then Right), or parallel sample read (Left and Right)
- Flexible CW-Link interface, which permits bridging to
standard interfaces (I2S, IBM CoreConnect™,
AMBA™ AHB, etc).
Applications:
Digital audio (CD, SACD, DVD-Audio), and multimedia systems (VCD, SVCD,
DVD, etc.).
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Deliverables:
- Detailed datasheet and user documentation for
system integration
- HDL testbench covering all functionalities of
the core and including automatic verification of the correctness of
the responses
- FPGA Netlist
- HDL (VHDL or VERILOG) source code
- Simulation script
Part Number: CWda16
Price:
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Implementation Results:
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Technology
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Structure
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Gate
Count
|
RAM
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Max.
Supported Audio Frequency
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Frequency
Imposed (cw_clk) |
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UMC 180 nm
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Basic Structure
|
6k
|
- |
384 KHz
|
200MHz
|
|
UMC 180
nm |
SUPPORT_DUAL32Bits
|
9k
|
- |
384 KHz
|
200MHz
|
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Family
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Example
Device
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Slices
|
IOB
|
GCLK
|
Mult18x18
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BRAM
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Max.
Supported Audio Frequency
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cw_clk
Fmax (MHz)
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Design
Tools |
|
Spartan-3E™
|
XC3S250E-4
|
328
|
137
|
3 |
- |
- |
384
KHz |
161
|
ISE 8.2.03i |
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Spartan-3™
|
XC3S400-4
|
302
|
137 |
3 |
- |
- |
384
KHz |
160
|
ISE
8.2.03i |
|
Spartan-IIE™
|
XC2S600E-6
|
243
|
137 |
3
|
- |
- |
384
KHz |
100
|
ISE
8.2.03i |
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Virtex-II
Pro™ |
XC2VP2-5
|
285
|
137 |
3
|
- |
- |
384
KHz |
193
|
ISE 8.2.03i |
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Virtex-II™
|
XC2V250-4
|
297
|
137
|
3 |
- |
- |
384
KHz |
185
|
ISE
8.2.03i |
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Virtex-4™
|
XC4VLX15-10
|
329
|
137 |
3
|
- |
- |
384
KHz |
225
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ISE 8.2.03i |
Basic Structure
|
Family
|
Example
Device
|
Slices
|
IOB
|
GCLK
|
Mult18x18
|
BRAM
|
Max.
Supported Audio Frequency
|
cw_clk
Fmax (MHz)
|
Design
Tools |
|
Spartan-3E™
|
XC3S250E-4
|
434
|
137
|
3 |
- |
- |
384
KHz |
167
|
ISE 8.2.03i |
|
Spartan-3™
|
XC3S400-4
|
392
|
137 |
3 |
- |
- |
384
KHz |
157
|
ISE
8.2.03i |
|
Spartan-IIE™
|
XC2S600E-6
|
330
|
137 |
3
|
- |
- |
384
KHz |
125
|
ISE
8.2.03i |
|
Virtex-II
Pro™ |
XC2VP2-5
|
357
|
137 |
3
|
- |
- |
384
KHz |
212
|
ISE 8.2.03i |
|
Virtex-II™
|
XC2V250-4
|
376
|
137
|
3 |
- |
- |
384
KHz |
155
|
ISE
8.2.03i |
|
Virtex-4™
|
XC4VLX15-10
|
450
|
137 |
3
|
- |
- |
384
KHz |
203
|
ISE 8.2.03i |
Support Dual 32-bit
Other Digital Audio IP Cores:
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IP Name/Part # |
Description |
| CWda03 |
SPDIF-AES/EBU to I2S Converter
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| CWda04 |
I2S to SPDIF-AES/EBU Converter
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| SPDIF-CWda14 |
Configurable SPDIF-AES/EBU Receiver |
| SPDIF-CWda15 |
Configurable SPDIF-AES/EBU Transmitter |
| I2S-CWda16 |
Configurable
Digital Audio Serial Input |
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I2S-CWda17 |
Configurable
Digital Audio Serial Output |
|
SDI-CWda41 |
SDI Audio De-embedder |
| SDI-CWda42 |
SDI Audio Embedder |
|
CWda30 |
3rd Order Stereo Digital Audio
Sigma-Delta Modulator
|
|
SRC-CWda50 |
Stereo / Mono Sample Rate Converter |
| SRC-CWda52 |
Multi-Channel Audio Sample Rate Converter (ASRC) |
|
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