Configurable Digital Audio Serial Output IP Core

Overview:

The CWda17 IP core is a configurable stereo audio interface component designed to output a serial digital audio stream. The CWda17 supports the well known I2S interface format originally developed by Philips and also the Left-Justified or Right-Justified serial audio formats.

The CWda17 can also be configured at runtime to support two (16, 20, 24 or 32 bit) audio channels written to two different addresses in an interleaved manner (this mode will be addressed in this document hereafter as “dual-channel-interleaving”), two 16-bit audio channels read in parallel from the same register address (hereafter described as “parallel-dual-channels write mode”), or one (16, 20, 24 or 32 bit) audio channel hereafter addressed as “singlechannel” write mode.

The audio samples are placed into a transmission FIFO using the Coreworks Link Interface (CW-Link) format. A runtime configurable output stage retrieves the samples from the FIFO and serializes the data to generate the serial audio stream (I2S, Left-Justified, and Right-Justified).

The FIFO input is clocked with the bus clock (cw_clk) unrelated to Fs (it must be clocked at a frequency above 2xFs when in dual-channel-interleaving mode, or above Fs for parallel-dual channels or single-channel write), and the FIFO output is clocked with the serial audio master clock (mclk) at a frequency of 256xFs, where Fs is the sample rate frequency.

Functional Description:

FIFO: This is a circular asynchronous first in first out RAM used to save audio samples. Its depth is configurable, and contains a register to indicate the number of words present in the FIFO at each moment. Attempts to write when it is full will assert high the cw-link_data_busy signal, and attempts to read when it is empty will be served, causing the last sample pair
present in the FIFO to be repeated.

Register File: Contains the configuration and information registers regarding the number of words currently in the FIFO, its maximum capacity, the programmable Upper FIFO Limit register, etc.

Configurable Serial Encoder: reads the audio samples from the FIFO and converts the CWlink audio stream into the desired output format. If the FIFO is empty, the last pair of samples, one for the left channel and the other for the right channel, is repeated until more samples are placed in the FIFO.

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