Multi-Channel Audio Sample Rate Converter (ASRC) IP Core
Overview:
The CWda52 is a Multi-channel
Asynchronous Audio Sample Rate Converter (ASRC). This core can be used
to interface digital audio equipment operating at different sample
rates. It has been designed for systems requiring very high quality in
terms of harmonic distortion and noise: it can realize most common
sample rate conversions with less than -120 dB of Total Harmonic
Distortion plus Noise (THD+N), having also a Dynamic range of 131 dB.
The CWda52 uses the Audio Parallel Interface (CWAPI) for the input
and output audio data, which permits bridging to other interfaces: I2S,
SPDIF-AES/EBU, AMBA, PowerPC (CoreConnect).
Functional Description:
Input Interface: receives the audio samples in the CWAPI format
and stores them in the FIFO RAM, providing the write address to that
module. There is one of these units per pair of channels.
Jitter Attenuator: measures the sample rate conversion ratio and
performs the synchronization necessary between the two different clock
domains with excellent jitter rejection. Also provides information
regarding the pointer of the initial read address to the RAM Address
Generator and to the Time Instants Generator at the beginning of the FIR
Filter convolution.
Time Instants Generator: generates the Time Instants used by the
Sinc(t) module, so that the correct coefficient set is used in the FIR
filter. It also generates some control signals used by the RAM Address
Generator module and by the Multiply Accumulate Unit.
RAM Address Generator: generates the addresses for the FIFO RAM
module to supply the correct set of audio samples to the FIR filter.
Sinc(t): this module can compute 229 values of a sinc(t) function
spanning 32 zeros. It outputs the coefficients used by the FIR filter.
FIFO RAM: it is circular first in first out RAM, organized in
such way as to store up to 4 pairs of audio channels, with a depth of
512 words for each audio channel. There is one of these units per pair
of channels.
Multiply Accumulate Unit: performs the multiply and accumulate
operation needed in one convolution cycle for each audio pair channel,
multiplexed in time. There is one of these units per pair of channels.
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Key Features:
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Deliverables:
Part Number: CWda52 Price:
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FPGA Implementation Results:
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Other Digital Audio IP Cores:
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