DDR 2 Memory Controller IP Core For
FPGA and ASIC
Overview:
The DDR2 SDRAM Memory Controller IP Core provides a high performance interface
to DDR2 SDRAM devices. The
DDR2 SDRAM Memory Controller IP Core accepts read and write commands using a
simple Local Interface and translate these
requests to the command sequences required by DDR2 SDRAM devices. The
IP core also performs all initialization and
refresh functions.
The DDR2 SDRAM Controller Cores Local Interface is implemented as a
queue that enables the Local Interface to
accept a new memory access request every clock as long as the queue is
not full. This enables the controller to
look ahead into the queue in order to better optimize throughput and
efficiency at the DDR2 memory device
interface.
The DDR2 SDRAM Controller IP Core uses bank management techniques to
monitor the status of each DDR2 SDRAM
bank. Banks are only opened or closed when necessary, minimizing access
delays. Up to eight banks can be
managed at one time. Access cascading is also supported, allowing read
or write requests to be chained together.
This results in no delay between requests, enabling up to 100% memory
throughput for sequential accesses.
The DDR2 SDRAM Controller IP Core is provided with run-time programmable
inputs for all timing parameters (CAS
Latency, tRAS, tRCD, tRRD, tRP, tRC, tRFC, tMRD, tXSNR, tFAW, tWR, tWTR,
tRTP)
as well as memory configuration
settings. This ensures compatibility with virtually any SDRAM
configuration. The core is also available with hard
coded timing and memory configuration parameters for designs requiring
low logic utilization or for designs
requiring high clock rate operation in slower FPGAs.
Core Deliverables:
· Core (Netlist or Source Code)
· Comprehensive Verification Suite (Source Code)
· Complete Documentation
· Expert Technical Support & Maintenance Updates
Available Optional Modules:
- Error Correction Coding (ECC) Module - can be used with the DDR2 SDRAM Controller Core to provide single bit correction and double bit detection.
- Read-Modify-Write (RMW) Module - can be used in conjunction with the ECC Module to handle non-word aligned bursts.
- Multi-Burst Module (MBM) - can be used with the DDR2 SDRAM Controller to extend the maximum burst length beyond the native burst length of the DDR2 SDRAM.
- Multi-port Front End
Main Features:
High performance access logic allows cascading of read and write
requests enabling up to 100% throughput for all DDR2 burst length settings (4, or 8)
Bank management logic monitors status of each SDRAM bank (up to 8
banks monitored) banks only opened or closed when necessary, minimizing access delays
Queue based user interface that enables the DDR2 SDRAM Controller Core
to look ahead in order to optimize the performance and throughput at the DDR2 SDRAM memory device
interface.
Pipelined design enables high clock rates with minimal routing
constraints
Supports 2T timing on the SDRAM control signals.
Configuration of SDRAM memory devices can be performed automatically
by controller or under user software control.
Supports all standard DDR2 SDRAM chips and DIMMs
Run-time configurable timing parameters CAS Latency (CL), tRAS, tRCD,
tRRD, tRP, tRC, tRFC, tMRD, tXSNR,
tFAW, tWR, tWTR, tRTP.
Full support for DDR2 additive latency modes (AL = 0 through AL = 5)
Full support for DDR2 on-die termination (ODT). Fully programmable
termination matricies for both reads and writes
Run-time configurable memory settings (i.e. row bits, column bits,
bank bits)
Supports up to eight chip selects
Support for DDR2 SDRAM device Self Refresh mode
Support for DDR2 SDRAM device Power-Down mode
Automatic generation of initialization and refresh sequences
Commands may be issued with or without SDRAM auto-precharge
selectable at each transaction request
Integrated data-path module for write DQS generation and read capture
Core datapath tailored to FPGA family and/or ASIC library
Size & Speed:
 |
Data Rate (Per Pin) | Clock Rate | Size |
 Xilinx Virtex-4 DDR 2 Evaluation Board |
|
| Virtex-5 | 666 Mbit/s | 333 MHz | 920 Slices | ||
| Virtex-4 | 533 Mbit/s | 267 MHz | 920 Slices | ||
| Spartan-3 | 333 Mbit/s | 167 MHz | 920 Slices | ||
| Virtex-II Pro | 400 Mbit/s | 200 MHz | 920 Slices | ||
| Virtex-II | 400 Mbit/s | 200 MHz | 920 Slices | ||
 |
Data Rate (Per Pin) | Clock Rate | Size | ||
| Cyclone II | 333 Mbit/s | 167 MHz | 1,950 LEs | ||
| Stratix II | 533 Mbit/s | 267 MHz | 1,950 LEs | ||
| Stratix | 400 Mbit/s | 200 MHz | 1,950 LEs |
|
|
 Xilinx Virtex-5 DDR-2 Evaluation Board |
|||||
| Device | Data Rate (Per Pin) | Clock Rate | Size | ||
| ASIC | >800 Mbit/s | >400 MHz | 13,700 Gates | ||
IP Core Price:
(A Virtex-5 loaner board is bundled with the IP core)
|
|
HiTech Global
Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124 USA
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com