DDR 3 SDRAM Memory Controller IP Core

Overview:

The Double Data Rate 3 (DDR3) SDRAM Memory Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

The core accepts commands using a simple local interface and translates them to the command sequences required by DDR3 SDRAM devices. The core also performs all initialization and refresh functions.

The core uses bank management techniques to monitor the status of each SDRAM bank. Banks are only opened or closed
when necessary, minimizing access delays. Up to eight banks can be managed at one time. A command queuing interface is
used enabling multiple, random address requests to be queued up, each with lengths as short as 4 DDR3 data cycles. This
architecture provides optimal bandwidth utilization both for cases of short transfers to highly random address locations as
well as cases of longer transfers to contiguous address space.

The core is provided with run-time programmable inputs for all timing parameters (tCL, tRC, tRCD, tRP, tMRD, tRRD, tRFC, tRAS) as well as memory configuration and refresh period settings. This ensures compatibility with all DDR2 SDRAM configurations.

Three optional add-on core are available:

  • Error Correction Coding (ECC)  - Provides single bit correction and double bit detection

  • Read-Modify-Write  (RMW) - Enables partial word writes when using ECC

  • Multi-Burst Core- Enables long burst length requests and handles address alignment for requests not aligned to the
    boundaries of the programmed burst length

  • Virtual FIFO - Converts a segment of memory to Virtual FIFO

  • Multi-Port Front End

DDR 3 SDRAM Memory Controller IP Core Features:

Command queuing and bank management enable up to 100% memory throughput
Supports auto-precharge commands for optimum random access performance
Achieves high clock rates with minimal routing constraints
Supports all standard DDR3 SDRAM chips and DIMMs
Run-time configurable timing parameters and memory settings
A variety of read capture options are supported
Automatic generation of initialization and refresh sequences
ECC, RMW and Multi-Burst add-on modules available
Supports self-refresh and powerdown modes
Source code available
Customization and Integration services

IP Core Deliverables:

Core (Netlist or Source Code)
Comprehensive Verification Suite (Source Code)
Complete Documentation
Expert Technical Support & Maintenance Updates

Speed & Size:

 Device    Version    Data Rate (per pin)    Clock Rate    Size  
 Virtex-5    Full Rate    666 Mbit/s    333 MHz    1,950 LCs  
 Virtex-5    Half Rate    666 Mbit/s    167 MHz    2,150 LCs  

Price: Quote Me

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