DF 6805 (8-bit FAST Microcontrollers Family) IP Core

General Description:

The DF6805 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6805 soft IP core is binary-compatible with the industry standard 68HC05 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6805:
- Harvard - where data and program buses are separated
- Von Neumann - with common program and data bus.
DF6805 has FAST architecture that is 4.1 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral functions.
The DF6805 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI), and can also be equipped with the Synchronous Serila Peripheral Interface (SPI).
The main 16-bit, free-running timer system has two input capture lines, and two output-compare lines.
Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.
Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6805 IP Core especially attractive for automotive and battery-driven applications.
DF6805 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Units

Control Unit
Control unit performs the core synchronization and data flow control. This module manages execution of all instructions. The STOP instruction and wakes-up the processor from the STOP mode.


Opcode Decoder
It performs an instruction opcode decoding and the control functions for all other blocks.


Bus Controller
Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic.


ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A), Condition Code Register (CCREG), Index register (X), and related logic such as arithmetic unit, logic unit, and multiplier.

Interrupt Controller
The extended Interrupt Controller has implemented 7-level interrupt priority control. The interrupt requests may come from external pin (IRQ) as well as from particular peripherals. The peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement established during reset. When interrupt condition occurs, an interrupt status flag is set to indicate the condition.

Timer with Compare Capture
The programmable timer is based on free-running 16-bit counter, plus input capture/output compare circuitry. The timer can be used for many purposes including measuring pulse length of two input signals and generating two output signals. The timer has 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contains the high and low byte of that functional block. Accessing the low byte of a specific timer function allows full control of that function, however, an access of the high byte inhibits that specific timer function until the byte is also accessed. Each of the input-capture channel has its own 16-bit time capture latch (input-capture regis-ter) and each of the output-compare channel has its own 16-bit compare register. Additional control bits permit software to control the edge(s) that trigger each input-capture func-tion and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer ac-tivities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of appli-cations although it is not as efficient as dedi-cated hardware for some specific timing applications.

I/O Ports
All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read.
Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out the port pins.

Watchdog Timer
The Watchdog Timer consist of free running timer CLK/213, plus control logic. The Watchdog Timer can be enabled by software by writing '1' to the WDOG Bit in MISC ($0C) register. Once enabled the WDT timer cannot be disabled by software. In addition the WDOG bit acts as a reset mechanism for the WDT Timer. Writing '1' to the WDOG Bit clears WDT counter and inhibits Watchdog timeout.

SCI
The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem.

 

DF6805 implementation results for ALTERA devices. The CPU features and Peripherals have been included.

DF6811 implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4	-3	1565/296	30

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