ASIC

DMAC - 10/100 Mb Ethernet Media Access Controller IP Core

General Description:
The DMAC is hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external PHY device enables network functionality in design. It is capable of transmitting and receiving Ethernet frames to and from the network. Half and full duplex modes are supported, as well 10 and 100 Mbit/s speed. The core is able to work with wide range of processors: 8, 16 and 32 bit data bus, with little or big endian byte order format. The DMAC provides static configuration of PHY IC. Design is technology independent and thus can be implemented in variety of process technologies. This core strictly conforms to IEEE 802.3 standard.

Key Features:

Conforms to IEEE 802.3-2002 specification
Configurable width CPU interface with little or big endianess:
    - 8-bit
    - 16-bit
    - 32-bit
Simple interface allows easy connection to CPU
Narrow address bus (4 bits) with indirect I/O interface to the transmit and receive data dual port memories
Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
Supports full and half duplex operation at 10 Mbps or 100 Mbps

CRC-32 algorithm:
    - calculates the FCS nibble at a time
    - automatic FCS generation and checking
    - able to capture frames with CRC errors if required
Lite design, small gate count and fast operation
Programmable MAC address
Promiscuous mode support
Allows operation from a wide range of input bus clock frequencies
Fully synthesizable
Static synchronous design
Positive edge clocking
No internal tri-states
Scan test ready

Applications:

Embedded microprocessor boards
Networking devices (Network Interface Cards, routers, switches)
Communication systems

Units

RX RAM Interface
Interfaces to external dual port memories used by the DMAC core to store received frames.

Receive module
This module is responsible for receiving frames from the Ethernet. Provides necessary functions for frame decapsulation, CRC checking, address recognizing and error detection.

Transmit module
Performs transmit management functions, sends frames to Ethernet medium. It is responsible for proper frame creation and response to PHY signals.

TX RAM Interface
Interfaces to external dual port memories used by the DMAC core to store transmitted frames.

Control and I/O logic
This module provides interface to CPU/BUS. It exchanges data and control logic with transmit and receive modules, thus controls these to perform transmit and receive operations. Proper data alignment and bytes order is performed inside this unit.
1 - data bus can be configured as 8-, 16- or 32- bit depends on processor’s bus size

Synchronization logic
There are 3 clock domains in the DMAC core. This module performs synchronization between these domains, and assures correct data exchange between these domains.

PHY Config
Provides a configuration of PHY device parameters such as speed setting, full or half duplex mode and others.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DMAC implementation results for ALTERA devices.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz] clk / rxclk / txclk
FLEX10KE	-1	1172 + 4KB RAM	160 /70 /55
ACEX1K	-1	1172 + 4KB RAM	180 / 70 / 55
APEX20K	-1	1172 + 4KB RAM	180 / 75 / 55
APEX20KE	-1	1172 + 4KB RAM	180 / 75 / 70
APEX20KC	-7	1172 + 4KB RAM	190 / 90 / 80
APEX II	-7	1172 + 4KB RAM	210 / 125/ 100
MERCURY	-5	1172 + 4KB RAM	250/ 120/ 100
STRATIX	-5	1150 + 4KB RAM	290 / 105/ 90
CYCLONE	-6	1172 + 4KB RAM	220/ 100/ 90

DMAC implementation results for XILINX devices.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz] clk/ rxclk/ txclk
SPARTAN-II	-6	625 + 4KB RAM	120 / 75 / 70
SPARTAN-IIE	-7	625 + 4KB RAM	120 / 75 / 70
VIRTEX	-6	625 + 4KB RAM	125 / 65 / 60
VIRTEX-E	-8	625 + 4KB RAM	165 / 85 / 65
VIRTEX-II	-6	625 + 4KB RAM	245 / 135 / 105
VIRTEX-II Pro	-7	625 + 4KB RAM	300 / 145 / 120

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124 - USA

Units

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist