Key Features:

► PCI Express Core Support
    o x1, x4, and x8  PCI Express Core (soft core)  
    o x1, x4, and x8 Xilinx PCI Express Endpoint Block Plus (Virtex 5 and Virtex 6 hard core)
► PCI-X Core Support
► PCI Core Support
► DMA Interface
    o Very flexible, easy-to-use, high-performance DMA implementation
    o Card-to-System (C2S) DMA Engine
         - Takes data from user logic and makes DMA Write Requests to 
            system memory
         - Demand-driven user interface; user can wait state for flow control  
         - Flexible Control - DMA Descriptor Engine fetches DMA 
           Descriptors from a linked list of Descriptors stored in system
           memory or user logic can directly control the DMA Engine
   o System-to-Card (S2C) DMA Engine
        - Makes DMA Read Requests from system memory, handles the
          resulting Read Completions, and forwards read data to user logic
        - Demand-driven user interface; user can wait state for flow control  
        - Guarantees read data ordering (re-orders completions that were
          received out of order)
       -  Flexible Control - DMA Descriptor Engine fetches DMA 
          Descriptors from a linked list of Descriptors stored in system 
          memory or user logic can directly control the DMA Engine
  o Base Configuration has 1 Card to System DMA Engine and 1 System
     to Card DMA Engine
  o Multi-Engine Configuration has 1-4 Card to System DMA Engines and
     1-4 System to Card DMA Engines
  o Engines are fully independent and are interleaved on a packet basis
  o 32-bit and 64-bit System Address Support
  o 32-bit and 64-bit Descriptor Linked-List System Address Support
  o Up to 64-bit Card Address Support
  o Designed for DMA destination which are FIFOs or addressed memory
  o MSI and Legacy Interrupt support
  o System address, Card Address, and Byte Count support byte
     alignment allowing for maximum software flexibility
  o Supports fragmented system and card memory
  o Supports extremely long Descriptor chains
 

 ► Master Interface (PCI Express Only)
  o Simple interface supports generation of Memory (32/64-bit 
      address),  I/O, Configuration (Root Complex implementations
      only), and Message (Msg/MsgD) transactions
  o Supports write and read transactions with up to one DWORD
     (32-bit) of payload data
► Target Interface
  o Very flexible, easy-to-use, high performance independent
     target write and read interfaces
  o Supports 32-bit and 64-bit Memory Base Address Registers
► Register Interface
  o Implements a 32-bit Memory Base Address Register for DMA
     and user registers
  o Half of Base Address Register space is reserved for user
     registers
  o Simple, fixed timing Register Interface makes adding user
     registers trivial
► Pre-integrated with other IP Cores to provide a full out-of-the-
    box system solution including:
  o Reference design using PCI Express/PCI-X/PCI Core, DMA
      Back-End Core, Multi-Port Front-End SDRAM Core, and
      example Target and Register logic
  o PCI Express/PCI-X/PCI Verification Suite
  o Windows XP/Vista Driver and Example Application
  o Linux Driver and Example Application

Price:

Related Products:

► PCI Express IP Core (Gen 1)
► PCI Express IP Core (Gen 2)