Multi-Standard DSP Acceleration Core Template

Multi-Standard DSP Acceleration Template IP Core

Overview:

The Multi-Standard DSP Acceleration Core is a fully customizable architecture template for acceleration of DSP algorithms. The IP core's architecture is based on a coarse-grained reconfigurable array and is optimized for the execution of nested program loops containing logic and arithmetic expressions. These loops are computationally expensive and common in many application domains.

The architectures derived from the template are able to compute one complete group of nested loops in each runtime configuration. The core has a functional unit array and an embedded memory array to provide highly parallel memory accesses and data operations. This allows the core to outperform DSPs and processors in intensive data processing.

The core is a low power solution for intensive data processing and it’s (re)configurability allows efficient use of the available hardware resources.

Functional Description:

Configuration Register File: This block contains the runtime configuration for executing a group of nested loops in a given core instance.

Configuration and Control I/F: This interface is used to reconfigure the core and to access control and status registers. The supported interfaces are CW-Link, AMBA™- APB and Coreconnect™ OPB.

Input and Output ports: The input interface is used to write the data to be processed and the output interface is used to collect the processed data. The supported interfaces are CW-Link, AMBA™-AHB and Coreconnect™-OPB.

Address Generator: This block computes the sequences of memory addresses for reading operands from the memories and writing the results back.

Read Crossbar: Configures the data path from memory unit outputs or system input ports to functional unit inputs. The read crossbar also allows routing the output of functional units directly into the input of other functional units.

Write Crossbar: Configures the data path from functional unit outputs to memory unit inputs or system output ports.

Memory Units (MU) Array: RAM or ROM embedded data memories used to store the data being processed or tables of constants, respectively.

Functional Units (FU) Array: Array of processing units chosen from a functional unit library. These units can be of any type and as many as required for the operations being executed.

Key Features:

Features available at pre-synthesis time:
• Configurable nested loop maximum depth
• Configurable number of input and output ports
• Configurable type and number of functional units
• Configurable type, number and capacity of embedded memory units
• Configurable data path width
• Configurable data path routing
• Configurable address generation capabilities

Features available at runtime:
• Reconfigurable data path
• Reconfigurable address generation

General features:
• Supports runtime partial reconfiguration using a memory mapped configuration register file addressable word by word
• CW-Link, Coreconnect™/OPB or AMBA™/AHB interface for data and configuration

Applications:

• Multimedia data compressing and decompressing
• Communications
• Digital signal processing in general

Deliverables:

Detailed datasheet and user documentation for system integration
HDL testbench covering all functionalities of the core and including automatic verification of the correctness of the responses
FPGA Netlist
HDL (VHDL or VERILOG) source code
Simulation script

Part Number: CWcomp03

Price:

How To Purchase

FPGA Implementation Results:

Family	Example Device	Slices	IOB	GCLK	Mult18x18	BRAM	Max. Clock Frequency	Design Tools
Spartan-3™	XC3S5000-4	1,949	461	1	8	configurable	66 MHz	ISE 9.2i
Virtex-II™	XC2V1500-4	1,969	461	1	8	configurable	87 MHz	ISE 9.2i
Virtex-4™	XC4VLX15-10	1,969	461	1	8	configurable	125 MHz	ISE 9.2i
Virtex-5™	XC5VLX50-1	1,198	461	1	8	configurable	158 MHz	ISE 9.2i

ASIC Implementation Results:

Technology	Gate count	Area	RAM	Max. Clock Frequency
UMC 130 nm	58 k	0.22 mm2	configurable	>166 MHz

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