On Chip Debugger For 8051, 80390, 8611, RPIC, and FPIC Microcontrollers

 

DoCDTM provides real-time and non-intrusive debug capability allowing a pre-silicon validation and post-silicon on chip software debugging.
DoCDTM is dedicated for all 8051/80390, and DRPIC/DFPIC core families. It allows hardware breakpoints, trace, variables watch, multi C sources debugging. The DoCDTM Debug Software can work as a hardware debugger as well as a software simulator. So some tasks can be validated at software simulation level, and after this step user can continue real-time debugging by uploading code into silicon.

System-on-Chip designs plagues keen problem with inaccessibility of important control and bus signals, because they lay often behind the physical pins of the device. It makes traditional measurement instrumentation useless. The best way to get around those limitations, for the verification tasks and software debug is using on-chip debugging tools. Other advantage of on-chip debugger is improving design productivity in integrated environment with graphical user interface. Ability to display/modify memories content, processor and peripherals register windows along with trace information, and ability to see the related C/ASM source code, are key for facilitation design process what surely increase productivity.


DoCDTM users can still use their favorite C compiler or assembler for software development, because the software supports most of High Level Object files produced by C/ASM compiler tools:

  • Extended OMF-51 produced by Keil compiler

  • OMF-51 produced by Tasking compiler

  • OMF-51 produced by Franklin compiler

  • Standard OMF-51 produced by some 8051 compilers

  • Extended OMF-251 produced by Keil compiler

  • NOI format file produced by SDCC-51 compiler

  • Intel HEX-51 format produced by each 8051 compiler

  • Intel HEX-386 format produced by each 80390 compiler

  • BIN format produced by each 8051 & 80390 compiler

The DoCDTM system consists of three major blocks:

  • Debug IP Core

  • Hardware Assisted Debugger

  • Debug Software

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The Debug IP Core is a real-time hardware debugger which provides access to  registers, memories and peripherals connected to  Dx8051/Dx80390/DRPIC/DFPIC IP Cores, and controls CPU work by non-intrusive method. The Debug IP Core is provided as VHDL or Verilog source code as well as CPLD/FPGA EDIF netlist depending on the customer requirements. DoCDTM provides a scaled solution, Because many SoC designs have both power and area limitations. Debug IP Core can be scaled to control gate count. The benefit is fewer gates for lower power and core size while trading off debug capability. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation) with a lesser feature set shipped in final silicon.

Features:

  •  Processor execution control

  •  Run, Halt

  • Reset

  • Step into instruction

  • Skip instruction

  • Read-write all processor contents

  • Program Counter (PC)

  • Program Memory

  • Internal (direct) Data Memory

  • Special Function Registers (SFRs)

  • External Data Memory

  • Code execution breakpoints

  • one real-time PC breakpoint

  • unlimited number of real-time OPCODE breakpoints (v 4.00 and above)

  •  Hardware execution watch-points

  •  two at Internal (direct) Data Memory

  • two at Special Function Registers (SFRs)

  •  two at External Data Memory

  • Hardware watch-points activated at a

  • certain address by any write into memory

  • certain address by any read from memory

  • certain address by write into memory a required data

  • certain address by read from memory a required data

  • Unlimited number of software watch-points

  • Internal (direct) Data Memory

  • Special Function Registers (SFRs)

  • External Data Memory

  •   Unlimited number of software breakpoints

  • Program Memory

  • Automatic adjustment of debug data transfer speed rate between HAD and Silicon

  • Communication interface

  •  JTAG interface - v4.00 and above

  • DTAG three wire communication - v3.xx

  • Fully static synchronous design with no internal tri-states

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The DoCDTM Software (DS) is a Windows based application. It is fully compatible with all existing 8051/80390 C compilers and Assemblers. The DS allows user to work in two major modes: software simulator mode and hardware debugger mode. Those two modes assure possibility to pre-silicon software validation in simulation mode and then real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions, or stopped at any of the breakpoints. The DoCDTM Debug Software supports all  8051/80390 (DR8051x, DR80390x, DP8051x, DP80390x) in the following architectures:

  • High Performance RISC - (DR -2 cycle)

  • Pipelined High Performance RISC - (DP -1 cycle)

Features:

  • In-system FLASH programming

  • Two working modes

  •  hardware debugger

  • software simulator

  • Source Level Debugging:

  • C level hardware/software breakpoints

  • C code execution

  • line by line

  • over line

  • out of function

  • skip line

  • ASM code execution

  • instruction by instruction

  • over instruction

  • out of function

  • skip instruction

  • ASM, C source view of code

  • Symbol Explorer provides hierarchical tree view of all symbols:

  • modules

  • functions

  • blocks

  • variables and more

  • Contents sensitive Watch window

  • Symbolic debug including:

  • code

  • variables

  • variable types

  • Unlimited number of Real-time hardware breakpoints

  • Program Memory (CODE)

  • Two real-time hardware watch-points for each space:

  • Internal (direct) Data Memory (IDM)

  • Special Function Registers (SFR)

  • eXternal Data Memory (XDM)

  • Unlimited number of software breakpoints

  •  Program Memory

  • Internal (direct) Data Memory (IDM)

  • Special Function Registers (SFR)

  • eXternal Data Memory (XDM)

  • Set/clear software or hardware breakpoints, watch-points in Disassembled and C Source Code windows

  • 1024 steps deep Software Trace

  • Load Program Memory content from:

  • OMF-51, extended OMF-51 files

  • OMF-251 file

  • Intel HEX-51, HEX-386 files

  • BIN file

  • Auto refresh of all windows during execution of program

  • Registers panel including ACC, B, PSW, PC, SP, DPTR, DPP and four banks of general purpose registers R0-R7

  • Internal (direct) Data Memory (IDM)

  • Special Function Registers (SFR)

  • eXternal Data Memory (XDM)

  • Timers/Counters

  • UARTs

  • I/O Ports

  • Dedicated windows for peripherals

  • Configurable auto refresh time period with 1s step resolution

  • Status bar containing number of actually executed instructions, number of clock periods and real processor speed rate

  • Hardware Assisted Debugger interface

  • JTAG interface

  • DTAG interface

  • The system runs on a Windows 98/Me/2000/XP PC

  • Supports software tools from Keil, Archimedes, IAR, Tasking, Franklin, SDCC and the others

 

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A high-performance Hardware Assisted Debugger is connected to the target system containing the DCD's core either in FPGA or ASIC. HAD is a small hardware adapter that manages communication between the Debug IP Core (JTAG protocol) inside silicon and a USB port of the host PC running DoCDTM Debug Software.


Features:

  • USB communication interface to target host at FULL speed

  • Synchronous communication interface to Debug IP Core

  • JTAG interface - Debug IP v4.00 and above

  • DTAG three wire interface - Debug IP v3.xx

  • Support three I/O voltage standards

  • 5.0 Volt systems

  • 3.3 Volt systems

  • 2.5 Volt systems

  • Single power supply directly from USB

  • Small physical dimensions

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    FLASH PROGRAMMING:

    All FLASH memory devices are supported by DoCD debug system. Such support is assured by configurability of FLASH programming algorithm, and supported devices database. New FLASH device can be easily added to existing base using build-in editor. DoCD debugger allows user to simply perform in-system programming of its FLASH memory without using any additional equipment. DoCD programming task is performed directly within Debug software, and after uploading of code, it is ready for debugging. Programming time is very short, and write operations are performed with maximal allowed speed by certain FLASH device.

    HARDWARE BREAKPOINTS:

    The number of hardware breakpoints is unlimited. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space. They stop program execution just prior an instruction pointed by Program Counter (PC). In the other words instruction located at the PC breakpoint address is not executed. The difference is found in the method of program execution. In this case program is run with full clock speed (in real-time), and processor is halted when hardware signalizes true breakpoint condition.


    HARDWARE WATCH-POINTS:

    The number of hardware watch-points is limited to six in different address spaces. Like software breakpoints, hardware execution watch-points can be set in direct RAM, SFRs and external RAM. They stop program execution after an instruction being executed. The difference is found in the method of program execution. In this case program is run with full clock speed (in real-time), and processor is halted when hardware signalizes true watch-point condition.

    SOFTWARE BREAKPOINTS:

    An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor. This means that breakpoints can be set in Program Memory space, direct RAM, SFRs and external RAM. If at least one software breakpoint is set program is executed in automatic step by step mode, with checking if certain breakpoint condition is met. Program execution is halted when breakpoint condition is already met, and its execution can be resumed at any time in any appropriate mode.


    MIXED MODE BREAKPOINTS:

    Mixed breakpoint mode is also allowed and it means that software and hardware breakpoints, and watch-points are mixed in the system. This gives user flexibility in the debugging. For example two different break conditions can be set using watch-points and hardware breakpoints. In each breakpoint mode halt means: CPU is halted and instructions are no longer being fetched, and all internal peripherals are also stopped (e.g. timers, watchdog). The UARTs work correctly in any case.

    SYMBOL EXPLORER:

    Symbol Explorer provides hierarchical tree view of all C project symbols. It supports all C types, variables, constants, functions, and symbolic names of registers. Along with watch window provides flexible and powerful debugging feature at high C language level.

    SCALED SOLUTION:

    Because many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size while trading off debug capability.

    HOST REQUIREMENTS:

    A Pentium class computer with minimum 32 MB of memory, 10 MB of free space on Hard Disk, CD-ROM drive, USB port, and Windows 98/Me or Windows 2000/XP operating system are required.

 



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