Error Correction Coding (ECC) Module IP Core
Overview:
Error Correction Coding (ECC) Module implements
an 8-bit error correction coding scheme for a 64-bit
data bus. The module enables single error correction (SEC)
and double error detection (DED). The module consists of an ECC generation path as well as ECC
detection and correction. ECC correction is possible for single
bit errors occurring in one of combined 72 data and check bits.
ECC detection is possible for errors in two of the combined 72
data and check bits.
Various status information is provided to the user including
whether an error was detected on a single bit or two bits. The
bit position of the error is provided for the case of a single bit
errors.
The ECC Module is designed for easy integration with memory controller cores
being offered by HiTech Global. Alternatively, the user
may integrate the module with their own custom memory controller
logic.
ECC Module IP Core Features:
- Implements 8-bit error correction code for 64-bit data bus
- Error check path implements single error correction (SEC) and double error detection (DED)
- Error flags provide data on what kind of error occurred (1-bit or 2- bit)
- Bit position of the error is provided for single-bit errors
- Pipelined design enables high speed operation
- Source code available
- Customization and Integration services available
IP Core Deliverables:
· Core (Netlist or Source Code)
· Comprehensive Verification Suite (Source Code)
· Complete Documentation
· Expert Technical Support & Maintenance Updates
Price:
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HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com