Extreme Low Latency 10G
Ethernet IP Solution
The 10Gbps Extreme Low
Latency Ethernet IP solution offers a fully integrated IEEE802.3
compliant package for NIC (Network Interface Card) and Ethernet
switching applications. This industry leading extreme low latency
solution in an extremely small footprint is specifically targeted for
demanding financial, high frequency trading, and high port count
networking / HPC applications.
Round Trip Latency of
24.9ns + Device Specific Transceiver Latency
As shown in the figure below, the 10Gbps Ethernet IP solution includes:
latency Ethernet; Tx = 7.8ns (user data in to line preamble out); Tx =
14.0ns (user data in to line data out), Rx = 10.9ns (line data in to
user data out)- ALL latency numbers include full FCS generation and
dependent transceiver wrapper for Intel (Altera) and/or Xilinx FPGAs
counter block (for RMON and MIB)
and I2C cores for external module and optical module status/control
A complete reference
design using a L2 (MAC level) packet generator/checker is also included
to facilitate quick integration of the Ethernet IP in a user design. A
GUI application interacts with the reference designís hardware elements
through a UART interface (a PCIe option is also available). An
application (with optional basic Linux PCIe driver/API) is also provided
for memory mapped read/write access to the internal registers.
MAC and PCS cores are
designed to take advantage of high performance 14/16/20nm FPGA devices
to achieve extreme low latency with a very small footprint.
As the PCS and transceiver wrapper is included with the Ethernet IP
solution, the line side directly connects the 10.3125Gbps FPGA
transceiver to the optical module (SFP+, XFP etc).
Ethernet IP solution implements two user (application) side interfaces.
The register configuration and control port can be 32-bit AXI4-Lite or
Avalon-MM interface. Depending upon the application layer, user can
select a configurable bit width AXI-4 Streaming or Avalon Streaming bus
to interface with the MAC block.
10Gbps Ethernet IP
supports advanced features like per- priority pause frames (compliant
with 802.3bd specifications) to enable Converged Enhanced Ethernet (CEE)
applications like data center bridging that employ IEEE 802.1Qbb
Priority Flow Control (PFC) to pause traffic based on the priority
● Implements the full 802.3 specification with preamble/SFD generation,
frame padding generation, CRC generation and checking on transmit and
● Implements 802.3bd specification with ability to generate and
recognize PFC pause frames.
● Implements reconciliation sublayer functionality with start and
terminate control characters alignment, error control character and
fault sequence insertion and detection.
● Deficit Idle Count (DIC) mechanism to ensure data rates of 10Gbps at
the transmit interface.
● Optional padding of frames if the size of frame is less than 64 bytes.
● Implements XON and XOFF Pause Frame (802.3 Annex 31A) generation and
termination providing flow control.
● Pause frame generation additionally controllable by user application
offering flexible traffic flow control.
● Support for VLAN tagged frames according to IEEE 802.1Q.
● Supports any type of Ethernet Frames such as SNAP/ LLC, Ethernet
II/DIX or IP traffic.
● Discards frames with mismatching destination address on receive
(except Broadcast and Multicast frames).
● Programmable Promiscuous mode support to omit MAC destination address
checking on receive path.
● Optional multicast address filtering with 64-bit Hash Filtering table
providing imperfect filtering to reduce load on higher layers.
● High speed CRC-32 generation and checking.
● Optional insertion of error control character in transmitted frame
● Programmable frame maximum length providing support for any standard
or proprietary frame length (e.g. 9K-Bytes Jumbo Frames).
● Status signals available with each Frame on the user interface
providing information such as frame length, VLAN frame type indication
● Optional padding termination on RX path for NIC applications or
forwarding of unmodified data to the user interface.
● Statistics indicators for frame traffic as well as errors (alignment,
CRC, length) and pause frames.
● Configurable bit width Avalon-ST or AXI4 Streaming user interface
● Implements statistics and event signals providing support for 802.3
basic and mandatory managed objects as well as IETF Management
Information Database (MIB) package (RFC 2665) and Remote Network
Monitoring (RMON) required in SNMP environments.
● Implements 10GBase-R PCS core compliant with IEEE 802.3-2008
● Implements 64b/66b encoding/decoding for transmit and receive PCS
using 802.3-2008 specified control codes.
● Implements 10G scrambling/descrambling using 802.3-2008 specified
polynomial 1 + x39 + x58.
● Implements 66-bit block synchronization state machine as specified in
● Implements Bit Error Rate (BER) monitor for monitoring excessive error
ratio. In addition, the core implements various status and statistics
required by the IEEE 802.3-2008 such as block synchronization status and
test mode error counter.
Licensing and Maintenance
● NO yearly maintenance fees for upgrades and bug fixes
● Basic core licensing for a single vendor (either Xilinx or Altera)
compiled (synthesized netlist) binary
● Other licensing options include:
o Vendor and device family agnostic source code (Verilog) license
The utilization summary of the 10G Ethernet solution is given in
following tables. The utilization numbers are best in class as compared
to other available 10G Ethernet cores with comparable feature set. The
Ethernet solution has been fully verified on different hardware
platforms for both Altera and Xilinx FPGAs and has also been verified
for interoperability with other 10G capable devices.
Performance (Tx And Rx
The performance of the 10G Ethernet solution is represented here in
terms of individual latencies of transmit and receive paths, i.e. the
time between the first bit of data input at 10G Ethernet MAC and the
first bit of data output at PCS- Transceiver interface.