FCRAM Memory Controller IP Core
Overview:
Fast Cycle Random Access Memory (FCRAM)
Controller is designed for use in applications requiring high memory
throughput, high clock rates and full programmability.
The core has been optimized to take advantage of the fast random cycle
and fast access times available with FCRAM.
The core accepts commands using a simple local interface and translates
them to the command sequences required by FCRAM devices. The controller
also performs all initialization and refresh functions. Access cascading
is supported, allowing
read or write requests to be chained together. This results in no delay
between requests, enabling up to 100% memory
throughput.
The core is provided with run-time programmable inputs for all timing
parameters as well as memory configuration settings.
This ensures compatibility with all FCRAM configurations.
Three
optional add-on modules are available:
· Error Correction Coding (ECC) Module - Provides single bit correction
and double bit detection
· Read-Modify-Write Module (RMW) - Enables partial word writes when using ECC
· Multi-Burst Module - Enables long burst length requests and handles
address alignment for requests not aligned to the
boundaries of the programmed burst length
Core Deliverables:
· Core (Netlist or Source Code)
· Comprehensive Verification Suite (Source Code)
· Complete Documentation
· Expert Technical Support & Maintenance Updates
| FCRAM Controller IP Core Features: · Access cascading enables up to 100% memory throughput
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Price:
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