Key Features:

o Conforms to v.2.1 of the I2C specification
o Master mode
   o Master operation
         o Master transmitter
         o Master receiver
   o Support for all transmission speeds
         o Standard (up to 100 kb/s)
         o Fast (up to 400 kb/s)
         o High Speed (up to 3,4 Mb/s)
    o Arbitration and clock synchronization
    o Support for multi-master systems
    o Support for both 7-bit and 10-bit addressing formats on the I2C bus
    o Build-in 8-bit timer for data transfers speed adjusting
o Slave mode
    o Slave operation
        o Slave transmitter
        o Slave receiver
    o Supports 3 transmission speed modes
        o Standard (up to 100 kb/s)
        o Fast (up to 400 kb/s)
        o High Speed (up to 3,4 Mb/s)
    o Allows operation from a wide range of input clock frequencies
    o User-defined data setup time

 

o User-defined timing (data setup, start setup, start hold, etc.)
o Simple interface allows easy connection to microprocessor/microcontroller devices
o Interrupt generation
o Fully synthesizable
o Static synchronous design
o Positive edge clocking and no internal tri-states
o Scan test ready  

Applications:

• Embedded microprocessor boards
• Consumer and professional audio/video
• Home and automotive radio
• Low-power applications
• Communication systems
• Cost-effective reliable automotive systems

Licensing Options:

Single Site license option is provided to companies designing in a single site.

Multi Sites license option is provided to companies designing in multiple sites.

Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.

Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction.

Price:

       Deliverables:

• Source code:
     - VHDL Source Code or/and
     - VERILOG Source Code or/and
     - Encrypted, or plain text EDIF
   

• VHDL & VERILOG test bench environment:
     - Active-HDL automatic simulation macros
     - ModelSim automatic simulation macros
     - Tests with reference responses

• Technical documentation:
     - Installation notes
     - HDL core specification
     - Datasheet

• Synthesis scripts

• Example application

• Technical support
     - IP Core implementation support
     - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
     - Phone & email support