Local Interconnect Network (LIN) bus controller IP Core

Overview:
The  Local Interconnect Network (LIN) bus controller IP Core provides single master with multiple slaves communication concept.
The LIN is a serial communication protocol designed primarily for use in automotive application. Compared to CAN, LIN is a slower but is simpler and more cost effective. It can be used in applications where events happen in “human time”. It is ideal for communication in intelligent sensors and actuators where the bandwidth and versatility of CAN is not required.

The LIN core provides an interface between a microprocessor/microcontroller and LIN bus. It can work as master or slave LIN node de-pending on work mode determined by microprocessor/microcontroller. The LIN controller supports transmission speed between 1kb/s and 20kb/s and can transmit and receive LIN messages compatible to LIN 1.3 and LIN 2.1. Reported status information includes the type and condition of transfer operations being performed by the LIN IP core, as well as wide range of LIN error conditions (overrun, framing, parity, timeout). The LIN includes programmable timer allows detection of timeout and synchronization error. The core is described at RTL level allowing target use in FPGA and ASIC technologies.

Key Features:
► Conforms with LIN 2.1 and LIN 1.3 specification.
► Automatic LIN Header handling
► Automatic Re-synchronization
► Data rate between 1Kbit/s and 20 Kbit/s
► Master and Slave work mode
► Time-out detection
► Extended error detection “Break-in-data” support

Functional Blocks:

Control State Unit
Control State unit is responsible for receiving frame from LIN bus. Provides necessary function for data reception, frame timing and error checking.

Host Controller Interface
Accepts inputs from the system bus and generates control signals for other DLIN functional blocks. Address bus ADDR(2:0) selects one of register to be read from/written into. Active level of RD, WR and CS can be configurable. RD and WR are ignored unless the DLIN has been selected by activating  CS input.

Baud Rate Generator
The LIN core contains a programmable 15 bit baud generator which divides clock input by a divisor in the range between 1 and (215-1). The output frequency of the baud generator is 32 x the baud rate. Two registers, called divisor latches DLL and DLH, store the divisor in the 15-bit binary format.

Receive Controller & Shift Register
Receive Controller is responsible for receiving frame from LIN bus. Provides necessary function for data reception, frame timing and error checking.

Data Buffer
Stores the receive or transmit data

Transmitter Controller & Shift Register
Performs transmit management function, sends data by LIN bus.

Interrupt Controller
Interrupt controller works with transmitter, receiver and control unit to indicate DLIN transmission events or errors. User can configure which events may generates interrupt by enabled or disabled corresponding bits in Interrupt Enable register. When interrupt was generated host can find information about reason by reading LIN Status Register.

Functional Blocks:

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