Mobile DDR SDRAM Memory Controller  IP Core For FPGA and ASIC

Overview: 

The Mobile Double Data Rate (DDR) SDRAM Controller IP Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

The core accepts commands using a simple local interface and translates them to the command sequences required by Mobile
DDR SDRAM devices. The core also performs all initialization and refresh functions.

The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to sixteen banks can be managed at one time.

The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.

The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This
ensures compatibility with all Mobile DDR SDRAM configurations.

Available Optional Modules:

• Error Correction Coding (ECC) Module (provides single bit correction and double bit detection)
• Read-Modify-Write (RMW) Module  (used in conjunction with the ECC Module to handle non-word aligned bursts)
•  Multi-Burst (MBM) Module (extends the maximum burst length beyond the native burst length of the SDRAM)
• Multi-Port Front-End

Core Deliverables:

• Core (Netlist or Source Code)
• Comprehensive Verification Suite (Source Code)
• Complete Documentation
• Expert Technical Support & Maintenance Updates

Main Features: 

• High memory throughput via Look-Ahead command processing, Bank Management and Auto- Precharge support
• Multi-Port Front-End for supporting high efficiency command reordering and multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard mobile DDR SDRAM chips
• Run-time configurable timing parameters and memory settings
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and power down modes

Size & Speed:                             

	Data Rate (Per Pin)	Clock Rate	Size
Virtex-5	333 Mbit/s	167 MHz	1,950 LCs
Virtex-4	333 Mbit/s	167 MHz	1,950 LCs
Virtex-II Pro	333 Mbit/s	167 MHz	1,950 LCs
Spartan-3 E	267 Mbit/s	133 MHz	1,950 LCs
Spartan-3	267 Mbit/s	133 MHz	1,950 LCs
	Data Rate (Per Pin)	Clock Rate	Size
Cyclone II	333 Mbit/s	167 MHz	1,950 LEs
Stratix II	333 Mbit/s	167 MHz	1,950 LEs
Device	Data Rate (Per Pin)	Clock Rate	Size
ASIC	>400 Mbit/s	>200 MHz	17,500 Gates

IP Core Price:        

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