Mobile SDR SDRAM Memory Controller IP Core
Overview:
The Mobile Single Data Rate (SDR) SDRAM Controller Core is designed
for use in applications requiring high memory throughput, high clock
rates and full programmability.
The core accepts commands using a simple local interface and translates
them to the command sequences required by Mobile
SDR SDRAM devices. The core also performs all initialization and refresh
functions.
The core uses bank management modules to monitor the status of each
SDRAM bank. Banks are only opened or closed when necessary, minimizing
access delays. Up to sixteen banks can be managed at one time.
The core queues up multiple commands in the command queue. This enables
optimal bandwidth utilization for both short transfers to highly random
address locations as well as longer transfers to contiguous address
space.
The core is provided with run-time programmable inputs for all memory
timing parameters and configuration settings. This
ensures compatibility with all Mobile SDR SDRAM configurations.
Available Optional Modules:
- Error Correction Coding (ECC) Module (provides single bit correction and double bit detection)
- Read-Modify-Write (RMW) Module (used in conjunction with the ECC Module to handle non-word aligned bursts)
- Multi-Burst (MBM) Module (extends the maximum burst length beyond the native burst length of the SDRAM)
- Multi-Port Front-End
Core Deliverables:
• Core (Netlist or Source Code)
• Comprehensive Verification Suite (Source Code)
• Complete Documentation
• Expert Technical Support & Maintenance Updates
Main Features:
• Multi-Port Front-End supports high efficiency command reordering and
multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard Mobile SDR SDRAM chips
• Run-time configurable timing parameters and memory settings
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and powerdown modes
• Source code available
Size & Speed:
 |
Data Rate (Per Pin) | Clock Rate | Size |
| Virtex-5 | 133 Mbit/s | 133 MHz | 1,100 LCs |
| Virtex-4 | 133 Mbit/s | 133 MHz | 1,100 LCs |
| Virtex-II Pro | 133 Mbit/s | 133 MHz | 1,100 LCs |
| Spartan-3 E | 133 Mbit/s | 133 MHz | 1,100 LCs |
| Spartan-3 | 133 Mbit/s | 133 MHz | 1,100 LCs |
 |
Data Rate (Per Pin) | Clock Rate | Size |
| Cyclone II | 133 Mbit/s | 133 MHz | 1,100 LEs |
| Stratix II | 133 Mbit/s | 133 MHz | 1,100 LEs |
|
Device |
Data Rate (Per Pin) | Clock Rate | Size |
| ASIC | >200 Mbit/s | >200 MHz | 10,000 Gates |
IP Core Price:
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HiTech Global
Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124 USA
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com