Multi Burst Memory Module IP Core

Overview:

The Multi-Burst Module interfaces with the DDR2, DDR and SDR SDRAM Controller Cores offered by HiTech Global. It enables read or write requests of 256 data cycles or more. It automatically partitions single requests into multiple smaller requests the size of the SDRAM’s programmed burst length. The Multi-Burst Module also automatically partitioning requests that are not aligned on the boundary of the SDRAM’s programmed burst length.

The Multi-Burst Module provides a simple user interface which is identical to SDR, DDR or DDR2 SDRAM Controller Cores. The maximum request size is typically configured for 256 data cycles. However, this can be configured to larger values at the expense of routing delay and resource usage.

The  Multi-Burst Module is offered as a standalone module or integrated with the DDR2, DDR, SDR, SDRAM Controller Cores.

Multi Burst Module IP Core Highlights:

• Automatically translates single requests up to 256 data cycles or more into multiple seamless requests to the SDRAM controller core
• Automatically partitions requests not aligned to SDRAM burst boundaries into multiple aligned seamless requests
• Simple user interface (identical to that of the SDRAM Controller Core)
• Pipelined design enables high speed operation
• Source code available
• Customization and Integration services available

IP Core Deliverables:
· Core (Netlist or Source Code)
· Comprehensive Verification Suite (Source Code)
· Complete Documentation
· Expert Technical Support & Maintenance Updates

Price:

www.HiTechGlobal.com

2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A
Tel : + 1 408 781-8043  
Fax: + 1 408 268-4173
info@hitechglobal.com