PCI Express IP Core for FPGA and ASIC

PCI-SIG Certified PCI Express IP Core

Overview:
The PCI Express Core provides a flexible, high-performance, easy-to-use Local Interface to the PCI Express Bus. The PCI Express Core implements all three layers defined by the PCI Express standard and supports all key PCI Express features. The core is available in numerous configurations including x1, x4, and x8 Lanes and support for numerous integrated and discrete PHYs. The core implements a PIPE interface which is customizable to support additional PHYs. The core is provided with a comprehensive Verification Suite with complete scripting and stimulus capabilities enabling the user design to be fully validated prior to use in hardware.

General Features:

► Endpoint, Root Port, or Endpoint/Root Port dual mode operation
► x1, x4, or x8 PCI Express Lanes
► 128-bit, 64-bit, and 32-bit Core Data Width (Core Data Width/Lanes optimized to silicon capabilities)

o 128-bit
    - x8 lanes, 125 MHz (high performance FPGA with low speed grade)
    - x4 lanes, 62.5 MHz (low cost FPGA)
o 64-bit
   - x8 lanes, 250 MHz (ASIC, high performance FPGA with high speed grade)
   - x4 lanes, 125 MHz (high performance FPGA with low speed grade)
o 32-bit
- x4 lanes, 250 MHz (ASIC)
- x1 lanes, 62.5 MHz (ASIC, all FPGAs)

► Extremely broad integrated and discrete PCI Express PHY support
   o Integrated PHY Support
     - ARM VSL212 (90nm)
     - Snowbush SBPCIE2000T90LP (90nm)
     - Altera S2GX
     - Altera Arria GX
     - Xilinx V5LXT/SXT
     - Xilinx V4FX
o External PHY Support
     - Genesys Logic GL9711 x1, GL9714 x4, GL9714 x8 (two GL9714)
     - Pericom PI7C9X1011A x1
     - Philips PX1011A x1
     - TI XIO1100 x1
o Generic PIPE x1/x4/x8
o Generic SERDES x1/x4/x8 (10bits/lane)
o Other PHYs supported on request
► Provided with comprehensive, source code PCI Express Verification Suite
► Provides a wealth of diagnostic information for superior system-level debug and link stability monitoring
► Complete error-handling support
► Supports up to six Base Address Registers and an Expansion ROM
► Supports user expansion of Configuration Space
► Easy to use
o Pre-decodes packets to provide key routing (BAR hits, Tag, etc.) information for the user
o Implements all aspects of the required PCIe Configuration Space; user can easily add custom Capabilities Lists and Configuration Registers via the Configuration Register Expansion Interface
o Automatically consumes all PCI Express Message packets and provides Message contents to the user on the simple Message Interface
o Implements Legacy/MSI interrupts automatically; user only pulls interrupt line up/down
o Achieves push-button timing with minimal routing constraints on all supported devices
o Control interface has consistent timing and function over all modes of operation
o User interfaces designed to connect directly to FIFOs
► Implements all 3 PCI Express Layers (Transaction, Data Link, Physical)
► Supports up to 8 Traffic Classes
► Source code available
► Customization and Integration services available
► PCI Express™ Base Specification Revision 1.1/1.0a compliant
► PCI SIG Compliance Certified


Xilinx Virtex-5 LX330T/FX200T/SX240T x8 PCI Express Development Board	Xilinx Virtex-5 LX110T/FX70T/FX100T/SX95T x8 PCI Express Development Board	Xilinx Virtex-5 LX155T/LX110T/FX70T/ FX100T/SX95T x4 PCI Express Development Board