Key Features:

► Endpoint, Root Port, or Endpoint/Root Port dual mode operation
► x1, x4, or x8 PCI Express Lanes
► 128-bit, 64-bit, and 32-bit Core Data Width (Core Data Width/Lanes optimized to silicon capabilities)

• PCI Express 5Gbps/lane
  • 128-bit
    o x8 lanes, 250 MHz (high performance FPGA)
    o x4 lanes, 125 MHz (high performance FPGA, low speed grade)
  • 64-bit
    o x8 lanes, 500 MHz (ASIC)
    o x4 lanes, 250 MHz (high performance FPGA)
  • 32-bit
    o x4 lanes, 500 MHz (ASIC)
    o x1 lanes, 125 MHz (ASIC, all FPGAs)

• PCI Express 2 5Gbps/lane
  • 128-bit
    o x8 lanes, 125 MHz (high performance FPGA with low speed grade)
    o x4 lanes, 62.5 MHz (low cost FPGA)
  • 64-bit
    o x8 lanes, 250 MHz (ASIC, high performance FPGA with high speed 
       grade)
    o x4 lanes, 125 MHz (high performance FPGA with low speed grade)
  • 32-bit
    o x4 lanes, 250 MHz (ASIC)
    o x1 lanes, 62.5 MHz (ASIC, all FPGAs)

► Extremely broad integrated and discrete PCI Express PHY support
   o Integrated PHY Support
     -  ARM VSL212 (90nm)
     -  Snowbush SBPCIE2000T90LP (90nm)
     -  Altera S2GX
     -  Altera Arria GX
     -  Xilinx V5 FXT
     -  Xilinx V4FX 
  o External PHY Support
  o Generic PIPE x1/x4/x8
  o Generic SERDES x1/x4/x8 (10bits/lane)
  o Other PHYs supported on request

 ► Provided with comprehensive, source code PCI Express Verification Suite
► Provides a wealth of diagnostic information for superior system-level debug and link stability monitoring
► Complete error-handling support
► Supports up to six Base Address Registers and an Expansion ROM
► Supports user expansion of Configuration Space
► Easy to use
  o Pre-decodes packets to provide key routing (BAR hits, Tag, etc.) information for the user
  o Implements all aspects of the required PCIe Configuration Space; user can easily add custom Capabilities Lists and Configuration Registers via the Configuration Register Expansion Interface
  o Automatically consumes all PCI Express Message packets and provides Message contents to the user on the simple Message Interface
  o Implements Legacy/MSI interrupts automatically; user only pulls interrupt line up/down
  o Achieves push-button timing with minimal routing constraints on all supported devices
  o Control interface has consistent timing and function over all modes of operation
  o User interfaces designed to connect directly to FIFOs
► Implements all 3 PCI Express Layers (Transaction, Data Link, Physical)
► Supports up to 8 Traffic Classes
► Source code available
► Customization and Integration services available
► PCI Express™ Base Specification Revision 1.1/1.0a compliant
► PCI SIG Compliance Certified

Price:

Related Products:

► DMA Back-End
► Complete PCI Express Solution

Xilinx Virtex-5 FX200T-2
 x8
PCI Express Development
Board