Key Features:

• x4 (Gen 1 & 2), x8 (Gen 1) PCI Express Core
• 64-bit data path at 2.5 and 5.0 Gbps per lane
• x8 Core (250 MHz) and 250 MHz frequency for 20 Gbps full-duplex bandwidth
• Suitable for Root Complex, Endpoint, Switch and dual mode / shared silicon
• PCI Express Base Specification Revision 2.0 and Revision 1.1 compliant (the core also supports PCI Express Base Specification Revision 1.0a)
• Up to eight Virtual Channels (VCs)
• Up to eight functions supported for Endpoint configurations
• Receive and Retry buffer size configurable
• Intel’s 8-bit PIPE interface to interface between the PHY MAC and PHY physical coding sublayer (PCS) /Physical Media Attachment (PMA) layers
• Fully compliant PHY PCS sub-layer (250 or 500 MHz)
• PHY PMA provided for Xilinx® Virtex™ 5 FXT & Altera® Stratix™ II GX
• Receive/transmit user Application Interface
• Input test port for enabling/disabling specific modes (such as remote boot or error generation)
• Output test port for monitoring (errors, state machine, and flow control)
• User clock

Customization

• Receive buffer changes allow configuration of a dedicated Receive buffer per VC or a single Receive buffer for all implemented VCs
• Easy customization with the IP Wizard
• The Wizard has built-in support for VHDL and Verilog
• User backdoor access to the PCIe Configuration Space Unused features are not implemented in silicon
• Full plug-and-play support

Data transfer

• Supports up to 4KB data payload transfer
• Supports all Memory, I/O, Configuration, and Message transactions
• Highly optimized Application interface for maximum effective throughput

Configuration

• Implements Type 0 Configuration space for Endpoint designs
• Implements Type 1 Configuration space for Root Complex, Switch, and Bridge designs
• Up to 6 BARs plus expansion ROM can be implemented for Endpoints
• All I/O and memory windows implemented for Root complex, Switch, and Bridge components

Power Management and Interrupt

• All Power State and associated logic implemented
• Legacy PCI Power Management support
• Native Active State Power Management L0s and L1 state support
• Power Management Event (PME message) and Beacon (Wake-Up) support
• MSI (up to 32, mapped to any TC) and INT message support
• MSI-X Capability Support
• Controlled easily by Application signals

Reference Design

• Master/target Application interface type for Endpoint and Root Complex designs
• Target connected to SRAM and registers
• Highly pipelined Master interface connected to SRAM module and data generator
• Provided as source code for free adaptation to user’s design
 

Price: