PCI Express Gen 3 IP Core

Overview:

The Core is compliant with the current PCI Express Base Specification Revision 3.0 (as well as Revisions 2.0 and 1.1). In combination with the DMA Back-end core and DMA driver, this core provides the maximum system throughput on a PCI Express Link.

The core is designed for ease of use including full receive packet decoding, complete error handling, automatic handling of PCI Express message packets and comprehensive system debug and link monitoring support.

The core is delivered fully integrated and verified with the user's target PHY. To accelerate simulations, the core is also delivered intergraded with a fast simulating behavioral PHY.

Key Features:

► Endpoint and Root Port
► x1, x2, x4, x8  and x16 PCI Express Lanes
► 8.0, 5.0, and 2.5 Gbit/s Serdes support
► Flexible Equalization support
► 32, 64, 128, and 256 bit core width to enable users to match the core speed with process capability
► Transaction Layer Bypass Option
► AER, ECRC, MSI-X, Multi-Vector MSI, Lane Reversal support

Price: Quote Me

Related Products:

► DMA Back-End
 

Development/Evaluation Boards:


Altera Stratix IV GT



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