x1 & x4 PCI Express PHY IP Core for ASIC & SOC
Overview:
1-lane and 4-lane PCI Express PHY Layer Controller IP cores
are in compliance with PCI Express Base Specification rev. 1.1a and
Intel’s PHY Interface for the PCI Express Architecture rev. 1.1.
The 1-lane PHY integrates one SerDes and the Physical
Coding Sublayer (PCS) which performs 8b/10b encoding and decoding,
elastic buffer
and receiver detection, data serialization and deserialization. The
SerDes supports an effective serial interface speed (2.5 Gb/s) of data
bandwidth, intended for use in ultrahigh-speed bi-directional data
transmission system.
The PHY IP core can also be externally configured for
various parallel bus width which is flexible and suitable for
implementation. It also supports four operational states for power
management to minimize power consumption. For production and self-test
purposes, the PHY IP core provides BIST andan internal loopback
capability.
The primary application of this IP is to provide very high-speed I/O
data channels for point-to-point baseband data transmission over an
on-chip termination resister of 50 Ohm +/- 10%.
This IP can also be used to replace parallel data transmission
architectures by providing a reduction in the number of traces,
connector pins, and transmit/receive pins. Parallel data loaded into the
transmitter is delivered to the receiver over a serial channel. It is
then reconstructed into its original parallel format. The maximum data
transfer rate in each direction is 256M bytes per second. It also offers
various power saving modes to significantly reduce power consumption as
well as scalability for a higher data rate in the future.
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Key Features: ► Complies with
PCI Express Base Specification rev. 1.1a. |
Deliverables:
Part Number: Price:
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HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124 - USA
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com