PCI To PCI Express Bridge IP Core

PCI To PCI Express IP Core (EZ IP Module)

The EZ IP Module is targeted to PCI designers making the shift to PCI Express and to experienced PCI Express designers looking for a robust yet simple PCI Express interface.

The EZ IP Module is built around PLDA's PCI-SIG compliant PCI Express IP Core. In addition to the three layers required by the protocol (Physical, Data Link, and Transaction), the EZ IP Module introduces a fourth. Based on a familiar PCI Backend interface, the EZ Layer automatically manages the complexities of the PCI Express protocol while serving as the only point of contact with the Application Layer.

The EZ IP Module is designed for Endpoint components and supports x1 and x4 Lane Configurations. It also supports Intel's PIPE specifications, is interoperable with the main PHY IPs, and includes built-in DMA channels

Features:

Native and Legacy Endpoint designs
1 Virtual Channel (VC)
Maximum payload size: 256 bytes
up to 6 BARs
Number of outstanding requests: 1, 2, 4, or 8
Application layer interface with up to 8 DMA channels
PHY
- Intel's PIPE interface (16-bit and 8-bit modes) between PHY MAC and PHY PCS/PMA
- PHY PCS/PMA provided for FPGA prototyping (Altera Stratix GX and Virtex 4 FX)
- PXPIPE interface (8-bit/250 MHz) for Philips PX1012A-EL1
Power Management
- All Power States
- Legacy PCI Power Management
- Native Active State Power Management L0s state
FPGA Limitations
- The EZ Core does not support the x8 configuration for FPGAs

Price:

Populated with Xilinx
Virtex-4 FX60/100

Populated with Xilinx Virtex-4 LX40/60/80/100/160

Populated with Altera Stratix GX25/40

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