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Key Features:
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PCI Express Core
o PCI Express Core (Gen 1
/ Gen 2) x1, x4, x8 or
Xilinx Virtex 5 PCI
Express x1, x4, x8 (hard core)
o High-performance, low-level PCI Express interface
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DMA Back-End Core
o High-performance multi-engine DMA
o High-performance Target and simplified Register accesses
o 64-bit address support, highly-customizable
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Memory Controller Core
o High-performance DDR3/DDR2/DDR
SDRAM Memory Controller
o Highest possible bus utilization; cascading, bank
management,
queued interface
o >333 (667Mb/s/pin) in FPGA; >=400 MHz (800Mb/s/pin) ASIC
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Multi-Port Front-End Core
o High-performance Memory Controller arbiter with request
prioritization and extended burst size
o Built-in Memory Self Test
o Enables user ports to be easily integrated into the
solution
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► PCI Express
Verification Suite
o Full-featured PCI Express Bus Functional
Model and simulation environment
o Self checking, native Verilog, easy-to-use
o Enables simple, powerful system simulations
o Provided with example scripts to test DMA,
Target, and Register accesses
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DMA Driver
o High-throughput DMA and Target access for
XP, Vista, and Linux
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PCI Express GUI
o PCI Express throughput characterization and
demonstration (Windows)
o DMA and Target command line example
application (Windows/Linux)
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Hardware Reference Designs
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