RLDRAM II 2 Memory Controller IP Core

RLDRAM II Controller IP Core

Overview:

The Reduced Latency DRAM (RLDRAM) II Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability.

The core has been optimized to take advantage of the fast random cycle and fast access times available with RLDRAM II.

The core accepts commands using a simple local interface and translates them to the command sequences required by
RLDRAM II devices. The controller also performs all initialization and refresh functions. Access cascading is supported,
allowing read or write requests to be chained together. This results in no delay between requests, enabling up to 100%
memory throughput.

The core is provided with run-time programmable inputs for all timing parameters as well as memory configuration settings.
This ensures compatibility with all RLDRAM configurations.

The core supports both common and separate data buses and multiplexed and non-multiplexed addressing.

Available Optional Modules:

Three optional add-on modules are available:

· Error Correction Coding (ECC) Module - Provides single bit correction and double bit detection
· Read-Modify-Write Module (RMW)- Enables partial word writes when using ECC
· Multi-Burst Module - Enables long burst length requests and handles address alignment for requests not aligned to the
boundaries of the programmed burst length

Main Features:

• Up to 100% throughput possible for read or write requests (not including refresh cycles) using Common Input / Output (CIO) RLDRAM II devices
• Up to 100% simultaneous read and write throughput possible (not including refresh cycles) using SeparatedInput / Output (SIO) RLDRAM II devices.
• Efficient bank management reduces random bank access latency – commands are executed immediately as long as tRC requirements are met.
• Pipelined design optimized for high clock rates and minimal routing constraints
• Integrated data-path for write data strobe (DK) generation
• Automatic Auto Refresh (AREF) command generation with programmable interval
• Programmable timing configuration – supports configurations 1, 2 and 3
• Supports burst lengths (BL) of 2 or 4
• Supports 288Mb and 576Mb RLDRAM II devices
• Support Multiplexed and Non-Multiplexed address interface to RLDRAM II devices
• Programmable selection for use of RLDRAM II on-die termination (ODT) and impedance matching resistance
• Supports x9, x18, and x36 devices in any combined data width (18, 36, 72, etc.)
• Available in Netlist or source code (Verilog, VHDL)
• Error Correction Coding (ECC) module available

Xilinx Virtex-4 RLDRAM Evaluation Board

Size & Speed:

	Data Rate (Per Pin)	Clock Rate	Size
Virtex-4	533 Mbit/s	267 MHz	380 Slices
Virtex-II Pro	400 Mbit/s	200 MHz	380 Slices
Virtex-II	400 Mbit/s	200 MHz	380 Slices

	Data Rate (Per Pin)	Clock Rate	Size
Stratix II	600 Mbit/s	300 MHz	800 LEs
Stratix	400 Mbit/s	200 MHz	800 LEs

Device	Data Rate (Per Pin)	Clock Rate	Size
ASIC	>800 Mbit/s	>400 MHz	5,600 Gates

IP Core Price:

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