RapidIO Controller IP Core

RapidIO Controller IP Core

Overview:
The RapidIO Interconnect Architecture, designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, is a high- performance, packet-switched, interconnect technology. The RapidIO addresses the high-performance embedded industry's need for reliability, increased bandwidth, and faster bus speeds in an intra-system interconnect. The RapidIO interconnect allows chip-to-chip and board-to-board communications at performance levels scaling to ten Gigabits per second and beyond.

The RapidIO controller IP core is designed to meet the growing needs of the industry. The core's simple, configurable and layered architecture is independent of applications, PHY designs, implementation tools and, most importantly, the target technology. The hardware and software configurable features make the core suitable for use in multiple applications. The design targets embedded systems, telecommunication, networking and any application where high speed, low latency response, low pin counts, reliability and scalability are necessary.

RapidIO IP Core Main Features:

Compliant with RapidIO specification, Revision 1.2
Supports both Serial and Parallel interfaces
Supports 1x and 4x serial interfaces at 1.25/2.5/3.125Gbps
Supports 8 and 16 bit parallel interfaces at 250/375/500 MHz
Implements physical, transport and logical layer functions
Supports both input/output and message passing protocols
Implements receiver controlled flow control
Supports all transaction flows and priorities
Support for up to 256 bytes data payload
Supports 34 bit addressing
Implements a flexible buffer management scheme
Performs link initialization, training, error detection and recovery
Performs auto detection of interface widths and modes
Supports multi-cast event control symbols
Targets FPGA, Structured ASIC and Standard Cell technologies

Configurable Options: Serial, Parallel or both interfaces Inclusion of messaging unit Buffer sizes Interface widths, modes and line rates Inclusion of user logic interface controller	Design Attributes: Highly modularr Fully synchronous Layered architecture Technology independent Scan friendly RTL Clearly demarked clock domains
Product Package: RapidIO RTL Code Verification environment Test cases Synthesis environment Training and Support	Documentation: Design guide Verification guide Synthesis guide
Availability: Now Language: Verilog HDL Synthesis: Synopsys/Synplify Simulation: Verilog-XL, NC Verilog, VCS Technology: 0.13u or better Price:
HiTech Global Design & Distribution, LLC 2059 Camden Ave. Suite # 160 San Jose, CA 95124 USA Tel : + 1 408 781-8043 Fax: + 1 408 268-4173 info@hitechglobal.com