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Multi-Tile Synchronization (MTS) Framework for HTG-ZRF8-R2 or HTG-ZRF-HH  ZYNQ UltraScale+ RFSoC platforms

Application Software and APIs interacts with the RFSOC via PCIe interface to control RF Data Converters (RFDC) and RF data playback/capture.

Multi-Tile Synchronization (MTS) function for DAC and ADC tiles is triggered by the RFDC Application/Driver to achieve the data synchronization on Multiple RF channels spread across multiple tiles.

Upto 32K samples/trigger with upto 1000 triggers/second Host-to-Card (H2C) user data transfer via Xilinx QDMA from input file to onboard memory for playback.

Upto 32K samples/trigger with upto 1000 triggers/second Card-to-Host(C2H) data capture to user application and into a file via Xilinx QDMA driver.

Frameworks save months of development and debug time by enabling developers to skip the tedious and time-consuming phase of IP core integration, interface verification and firmware/software development. 

Key Framework Features

  Clocking schemes supporting Multi-Tile and Multi-board synchronization

  External reference clock to synchronize multiple boards for data playback and capture

  Supports External RF sample clock phase-locked to external reference clock

  External trigger phase-locked to external reference clock for RF playback and capture

  Supports data transfer from Host Computer to the onboard Memory via PCIe interface using Xilinx QDMA IP

  Custom FPGA IP for simultaneous multi-channel data playback/capture from/to onboard memory

  Xilinx Zynq RFSOC ARM configuration with UBoot and Petalinux support

  Software and APIs for FPGA, RFDC and playback/capture controls

  QDMA application software and APIs for data playback and capture

  Lowest startup cost for developing complete RF solution with Xilinx UltraScale+ RFSOC

  Simplified, single-sourced licensing for all FPGA IP cores and RFSOC components


Framework Components

PCIe Interface:

RFSOC Control and Management:  QDMA AXI-Lite interface is used for the RFDC and other IP control/status. The HTG-RFSOC implements a general-purpose register file for various control/status and statistics counters. Access to the registers are 32-bit wide and is provided through the QDMA driver via the PCIe interface.

DMA: The framework comprises of a Xilinx QDMA subsystem that is responsible for DMA transfers between the Host PC and the board. These transfers and the host interface is provided via the PCIe interface on the Host PC  

RF Playback and Capture:

RF Playback: Once the samples have been transferred from the Host PC onto the onboard memory, FPGA logic reads samples from the onboard memory and stores them in a cache. Upon receiving a trigger, the data from the cache is played on the streaming interface to Xilinx RF Data Converters IP where these digital samples are converted to analog samples and driven to output Analog ports via DAC interfaces.  

RF Capture: Analog samples are received by the Xilinx RF Data Converters IP from input Analog ports via ADC
interface. These analog samples are converted to digital samples and placed on the ADC streaming
interface. The on the streaming interface is first written to the cache and then transferred to the onboard memory.

RFSOC ARM: RFSOC PS is configured with UBoot and Petalinux. Basic APIs and tools to access RFSOC PL are also provided in the framework package.

Software, Drivers and APIs: Application software for QDMA and RFSOC along with the APIs are provided as a source in the framework package.




Multi-Tile Sync Example Project:

 A working RFSOC builds and images are provided for out-of-the-box testing of Multi-Tile synchronization, etc. on the target RFSOC Board. In addition to a working build, a TCL script based Xilinx Vivado project generation is provided with Xilinx Block Designs (BD) for the following key components:

1.  Xilinx QDMA Subsystem for PCI Express.

2.  Xilinx Zynq UltraScale+ RF Data Converter with Multi-Tile sync and required clocking for the target RFSOC Board.

3.  Xilinx DDR4 SDRAM (MIG) for onboard SODIMM on RFSoC Programmable Logic (PL).

4.  Xilinx Zynq UltraScale+ MPSOC Processing System (PS) with interconnects.


  The framework package contains all of the required ingredients for Multi-tile synchronization to work out-of-the-box on the RFSOC board. The framework contains files such as:

  1) UBOOT device-tree and compiled image files.

  2) Kernel device-tree and compiled image files based on PetaLinux OS.

  3) Root-filesystem based on PetaLinux OS.

  4) A pre-configured .WIC image which easily loads on an SD-Card.

  5) A sub-package consists of files which can be easily flashed in the RFSOC's QSPI flash partitions.

  6) Extensive documentation which outlines each step and command to be executed to get the RFSOC ARM up and running.

Software, Drivers and APIs:

  The framework package contains all the required application and software for QDMA and RFSOC along with the APIs. The source code of each utility, API and driver is also provided with the package.

  1) A tool to read and write FPGA registers and memory interfaces from PS subsystem.

  2) A tool to program and configure the on-board PLL from PS subsystem.

  3) A tool to directly access on-board PLL registers using I2C interface from PS subsystem.

  4) Tools to read system monitoring information from both PS subsystem and Host PCIe interface.

  5) Tools to program and configure RF Data converters according to designated latency from both PS subsystem and Host PCIe interface.

  6) A central tool to talk to kernel drivers and initialize userspace queues and channels to control RF data capture and Playback.

  Along with above userspace utilities, kernel space driver is also provided with the framework package. The driver is responsible to handle the kernel interfaces and QDMA transfers for RF data Capture and Playback operations.

  The framework package also includes a number of Bash and Python scripts to assist user in performing multiple handy operations. The packages includes:

  1) A bash script to initialize the RFSOC board and program on-board PLL after ARM boot-up.

  2) A Python script to generate a number of mathematical curves, such as Sine, Impulse, Cosine to name a few, in hex and LVM formats to be used with RF data Playback and Capture interfaces.

  3) A Python script to plot multiple mathematical curves in graphical form.

  4) An extensive test suite developed to validate the complete operation of RFSOC board and, primarily, to verify the synchronization among all of the ADC channels. The suite consists of multiple scripts.

  5) Scripts to read FPGA counters and different statuses for debugging purposes.


Ordering Information:

Part Number: HTG-ZRF8-MTS
Price : Contact us