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Serial ATA  (SATA) I/II/III Device IP Core

General Description

The Serial ATA Device Controller IP Core is fully  compliant to the Serial ATA 3.0 specification and provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.

Features:

10/20/40 bit Phy interface
Connects to SAPIS compliant serial ATA Phy
Fully compliant to SATA Gen 1 (1.2 Gb/s) , Gen 2 (2.4 Gb/s), and Gen3 (6.0 Gb/s)
Wishbone slave interface for register access and FIFO/DMA data transfers
Only very few FF's in the Phy clock domain, main part on the Wishbone clock
128 byte (32 double word) data FIFO (optional 256 byte)
Parallel ATA legacy software compatibility
Implements the Task File, the non-standard serial ATA status and control registers, specific device registers and native mode registers
interrupt and DMA handshake (external DMA)
48-bit address feature set supported
8b/10b coding and decoding
CONT and data scramblers to reduce EMI
CRC generation and checking
Auto inserted HOLD primitives
Power management support (partial and slumber)
Optional native mode programming model

Functional Description:

The Serial ATA Link and Transport Layer Core implements a serial ATA device interface which connects to a SATA PHY via a 10bit interface and provides a WISHBONE slave interface for register and DMA access. It consists of the link layer module - with 10/20/40 bit data paths to the physical layer - and a transport layer module which connects to the system via a WISHBONE slave interface.

SAPIS PHY Interface
This interface connects to any SAPIS compliant serial ATA PHY. Power management and speed negotiation signals are included. The PHY interface is synchronous to the PHY clock domain, which may have a different clock frequency than the system clock domain. Synchronization is done by the Serial ATA Link and Transport Layer Core.

System Slave Interface
The slave interface is used to access all core internal registers as well as the data FIFO. Software or an external DMA unit can write transmit data into the data FIFO or can read from the FIFO.

DMA Handshake
Simple handshake signals are provided to connect a DMA unit to the core module. The DMA requests will be asserted as soon as any transmit data is available or is needed in the core's data FIFO. The DMA unit will then access the data FIFO via the Wishbone slave interface. A system interrupt will inform host software on completion of a data transfer.

Automatic flow control mechanisms control data throttling to avoid underflow or overflow of the transmit data FIFO. The DMA unit (or host software) may work at any speed without the risk of data loss. Data FIFO thresholds can be adjusted to optimize the data flow control.

System Interface can Wishbone, OPB, or AHB

Utilization & Speed

Family

 Spartan-6

Example Device

XC6SLX45T-2

Fmax  (MHz)

 >120

Slices

 939

IOB

4

GCLK

 3

BRAM

1

MULT

 0

DCM/ DLL

 1

GTP/ GTX

 1

Design Tools

     ISE 13.2

Virtex-6

XC6VLX240T-1

>150

886

4

3

1

0

1

1

ISE 13.2

Virtex-5

XC5VFX70T-2

>130

1043

4

3

1

0

1

1

ISE 13.2

Kintex-7

XC7K325T-1

>190

1004

4

3

1

0

1

1

ISE 14.1

Virtex-7

XC7VX485T-2

>200

1143

4

3

1

0

1

1

ISE 14.1

Zynq

XC7Z045-2

>190

1068

4

3

1

0

1

1

ISE 14.1