SPI Flash Controller Wishbone Bridge
IP Core
SPI-Flash/WISHBONE bridge allows communication between a SPI-Flash
and WISHBONE host. The SPI Flash Controller IP Core is able to translate
WISHBONE 32 bit read commands to SPIFlash with PSI mode 3 (CPOL=1, CPHA=1)
(ST, SST, Spansion and Nexflash or FLASH device with the same commands
and protocol). It responds to read command by reading 4 bytes from the
FLASH device. The host can also directly boot from an attached FLASH
device.
The FLAHS Device is mapped in to a window in on the WISHBONE bus, where
it can be easily accessed in a truly random fashion. This window can be
resized and moved across the entire FLASH space at any time.
The FLASH devices can be easily erased and reprogrammed by issuing
appropriate commands to the flash devices..
Main Features:
- Supports up to 8 FLASH Devices on a single SPI bus
- Supports FLASH devices up to 16MBytes each
- Flash is directly memory mapped in to the SoC memory space
- Supports high speed FLASH devices, up to 50 Mhz
- Can directly boot from FLASH after power on
- Software assistant FLASH programming
- SoC Interface: AVALON, AHB, OCP, OPB, PLB, WISHBONE, Customer specified bus interface
- No dedicated local memory required
- Compact and cost-effective solution for embedded applications
Architecture:
Size & Speed:
Sample Synthesis results for SPI Flash Controller IP Core. The goal was smallest and fastest implementation.
| Technology | Gate Count | Operating Frequency |
| UMC 0.18 um | 6,600 gates | 50MHz SPI, > 250 MHz Wishbone |
| Xilinx Virtex 2 1000-5 | 3,000 LUTs | 50MHz SPI, > 140 MHz Wishbone |
Price:
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