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Spacewire Codec
IP Core
Overview:
This IP core implements a Spacewire Codec with RMAP support
and AMBA host interface. The core implements the Spacewire standard with
the protocol identification extension (ECSS-E-50-12 part 2) and Remote
Access Memory Protocol (RMAP) protocol draft C. Receive and transmit
data is autonomously transferred between the Spacewire Codec and the
AMBA AHB bus using DMA transfers. Through the use of receive and
transmit descriptors, multiple Spacewire packets can be received and
transmitted without CPU involvement. The GRSPW control registers are
accessed through an APB interface. For critical space applications, a
fault-tolerant version of this IP core is available with full SEU protection of
all RAM blocks.
The Spacewire IP core is configured through a set of
registers accessed through an APB interface. Data is transferred through
DMA channels using an AHB master interface. Currently, there is one DMA
channel but the core can easily be extended to use separate DMA channels
for specific protocols.
There are three clock domains: one for the AHB interface (system clock),
one for the transmitter and one for the receiver. The receiver clock can
be twice as fast and the transmitter clock four times as fast as the
system clock whose frequency should be at least 10 MHz. The core only
supports byte addressed 32-bit big-endian host systems.
The Spacewire IP corecan be split into three main parts:
the link interface, the AMBA interface and the RMAP handler.
- The link interface
consists of the receiver, transmitter and the link interface FSM. They
handle communication on the SpaceWire network.
- The AMBA interface consists
of the DMA engines, the AHB master interface and the APB interface. The
link interface provides FIFO interfaces to the DMA engines. These FIFOs
are used to transfer N-Chars between the AMBA and SpaceWire domains
during reception and transmission.
- The RMAP handler is an
optional part of the Spacewire IP core which can be enabled with a
generic. It handles incoming packets which are determined to be RMAP
commands instead of the receiver DMA engine. The RMAP command is decoded
and if it is valid, the operation is performed on the AHB bus. If a
reply was requested it is automatically transmitted back to the source
by the RMAP transmitter.

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►Price:

How To Purchase
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►Implementation
Results:
(Cells / RAM blocks / AHB
MHz / SPW MHz)
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Core configuration |
RTAX |
Virtex2
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ASIC
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| GRSPW |
2,800 / 2 / 40 /
100
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1,900 / 3 / 80 /
200
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10,000 gates
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GRSPW + RMAP
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3,600 / 2 / 40 /
100
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2,800 / 3 / 80 /
200
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15000 gates |
GRSPW-FT
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2,900 / 4 / 40 /
100
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2,000 / 6 / 80 /
200
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11,000 gates |
GRSPW-FT + RMAP
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3,700 / 4 / 40 /
100
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2,900 / 6 / 80 /
200
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16,000 gates |
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