16950 Configurable UART with FIFO IP Core

General Description:

The 16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the OX16C950. The 16950 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activated allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. 16950 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16950 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. The D16950 has complete MODEM-control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link. 16950 core includes all 16450, 16550, 16650 and 16750 features and additional functions. 16950 has ICR registers that gives additional capabilities of configuration of UART work. Data transmission may be synchronize by external clock connected to RI ( for receiver and transmitter) or to DSR ( only for receiver) pin. NMR register allows to enable 9-bit mode transmission with or without special character. Writing and reading from/to FIFO may be controls by trigger level registers. Trigger level registers may be set any value from 1 to 127.

The 16950 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The 16950 is a technology independent design that can be implemented in a variety of process technologies.

In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals.

The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface 16950 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

Units

Receiver Control

Receiving starts when the falling edge on Serial Input (SI) during IDLE State is detected. After starting the SI input is sampled every 16 internal baud cycles as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state.

Receiver FIFO

The Rx FIFO is 16 levels (16550) or 64 levels (16750) deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. Any more data entering the Rx shift register will set the Overrun Error flag.

Transmitter FIFO

The Tx portion of the UART transmits data through SO as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO if it is currently full. Loading to the Tx FIFO will again be enabled as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.

Transmitter Control

Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator (the worst case delay is: 1 baudout cycle) after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.

Data Bus Buffer

The data Bus Buffer accepts inputs from the system bus and generates control signals for the other D16950 functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low, and are qualified by CS; RD and WE are ignored unless the D16950 has been selected by holding CS low.

Modem Control Logic

Modem Control Logic controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).

Baud Generator

The 16950 contains a programmable 16 bit baud generator that divides clock input by a divisor in the range between 1 and (216–1). Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the 16950 in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM to prevent long counts on initial load. In addition prescaler register is provided which can further divide the clock by values in the range 1,0 to 31,875 in steps of 0,125. Other additional is Time Clock Register (TCR) which allows set the sampling clock between 4 and 16 values. This options of baud rate capable any input clock frequency up to 60MHz.

Interrupt Controller

16950 consists fully prioritized interrupt system controller. It is enabled by INTSEL pin. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Status (ISR) registers.

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