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USB 3.0 SuperSpeed Device IP Core

Overview:

A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of a USB Device interface.

Simplified Block Diagram

Main Features: 

►USB 3.0 SuperSpeed support, 5Gbit/s
►USB 3.0 PIPE interface support
►Virtex 5/6 GTX transceiver support
►Integrated DMA engine
►Full duplex operation support
►Up to 16 fully configurable endpoints
►Bulk, control, interrupt and isochronous transfers
►Automatic Link Control and Management performed in hardware
►User transparent error recovery and re-transmission of packets
►Automatic Power State transition performed in hardware (all power states are supported)
►Autonomous operation with very little firmware interaction
►System Interface:
    -AHB, AVALON, OCP, OPB, PLB ,WISHBONE, and Customer specified bus interface
► Compact and cost-effective solution for SoC

 

Architecture:

The USB 3.0 Device IP Core, implements all required functions to transport USB 3.0 traffic. This includes the PHY Layer, which implements support functions required to talk to a USB 3.0 PIPE complaint PHY interface; The Link and Protocol layers that implement the USB 3.0 link management, transaction management and data transfers; and the Transport Layer, which provides and interface to external interfaces.